{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,8]],"date-time":"2026-07-08T06:19:47Z","timestamp":1783491587376,"version":"3.55.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:00:00Z","timestamp":1780444800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T00:00:00Z","timestamp":1780444800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003032","name":"Association Nationale de la Recherche et de la Technologie","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003032","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,6,3]]},"DOI":"10.1109\/async69614.2026.00023","type":"proceedings-article","created":{"date-parts":[[2026,7,7]],"date-time":"2026-07-07T19:43:21Z","timestamp":1783453401000},"page":"92-96","source":"Crossref","is-referenced-by-count":0,"title":["74% Power Reduction in Bundled Data Circuits Thanks to Clock Gating Integration"],"prefix":"10.1109","author":[{"given":"Adrien","family":"Godard","sequence":"first","affiliation":[{"name":"Univ. Grenoble Alpes,CNRS, Grenoble INP**, TIMA,Grenoble,France,F-38000"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Robin","family":"Wilson","sequence":"additional","affiliation":[{"name":"STMicroelectronics,Crolles,France,F-38920"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sylvain","family":"Engels","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes,CNRS, Grenoble INP**, TIMA,Grenoble,France,F-38000"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Laurent","family":"Fesquet","sequence":"additional","affiliation":[{"name":"Univ. Grenoble Alpes,CNRS, Grenoble INP**, TIMA,Grenoble,France,F-38000"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3375350"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2030436"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/43.980258"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICEDSS.2018.8544281"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICICICT1.2017.8342527"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3464870"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00020"}],"event":{"name":"2026 30th International Symposium on Asynchronous Circuits and Systems (ASYNC)","location":"Kgs. Lyngby (Copenhagen), Denmark","start":{"date-parts":[[2026,6,3]]},"end":{"date-parts":[[2026,6,5]]}},"container-title":["2026 30th International Symposium on Asynchronous Circuits and Systems (ASYNC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11594429\/11594446\/11594568.pdf?arnumber=11594568","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,8]],"date-time":"2026-07-08T06:00:58Z","timestamp":1783490458000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11594568\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,6,3]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/async69614.2026.00023","relation":{},"subject":[],"published":{"date-parts":[[2026,6,3]]}}}