{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T11:01:42Z","timestamp":1730199702512,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ats.2002.1181703","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T11:35:00Z","timestamp":1056627300000},"page":"151-156","source":"Crossref","is-referenced-by-count":0,"title":["Tests for word-oriented content addressable memories"],"prefix":"10.1109","author":[{"family":"Zhao Xuemei","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ye Yizheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chen Chunxu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"48","article-title":"Built-in Self Test for Content Addressable Memories","author":"kang","year":"0","journal-title":"Computer Design VLSI in Computers and Processors 1997 ICCD '97 Proceedings"},{"key":"ref3","first-page":"70","article-title":"Functional Testing of Content-Addressable Memories","author":"lin","year":"1998","journal-title":"Proc IEEE Intern Workshop Memory Technology Design and Testing"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655905"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1998.670899"},{"key":"ref5","article-title":"TLB\/CAM Test Pattern Specification","author":"balakrishnan","year":"1998","journal-title":"CAD LSI Logic"},{"key":"ref8","article-title":"Testing SRAM-based content addressable memories","volume":"40","author":"zhao","year":"2000","journal-title":"IEEE Transaction on Computer"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.1994.397199"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19970020"},{"key":"ref9","article-title":"Inorougn Testing of Any Multi-port Memory with Linear Tests","volume":"21","author":"van de goof","year":"2002","journal-title":"IEEE Trans Comput Aided Design Integ Circ Syst"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.1994.397193"}],"event":{"name":"Eleventh Asian Test Symposium","acronym":"ATS-02","location":"Guam, USA"},"container-title":["Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8413\/26519\/01181703.pdf?arnumber=1181703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T20:11:47Z","timestamp":1489435907000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1181703\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/ats.2002.1181703","relation":{},"subject":[]}}