{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T22:14:41Z","timestamp":1776204881040,"version":"3.50.1"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,12,17]]},"DOI":"10.1109\/ats64447.2024.10915226","type":"proceedings-article","created":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T17:45:02Z","timestamp":1741974302000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Design and Simulation of Fault Detection Technique for NAND Based Memory Array"],"prefix":"10.1109","author":[{"given":"Jamuna","family":"S","sequence":"first","affiliation":[{"name":"DSCE,Department of Electronics and Communication Engineering,Bengaluru,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Madhura","family":"R","sequence":"additional","affiliation":[{"name":"DSCE,Department of Electronics and Communication Engineering,Bengaluru,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kishore Kumar","family":"K","sequence":"additional","affiliation":[{"name":"DSCE,Department of Electronics and Communication Engineering,Bengaluru,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Murali S","family":"Bharadwaja","sequence":"additional","affiliation":[{"name":"DSCE,Department of Electronics and Communication Engineering,Bengaluru,India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-94-007-6082-0","volume-title":"Flash Memories: Economic Principles of Performance, Cost, and Reliability Optimization","author":"Richter","year":"2014"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-5146-0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2022.3229281"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.32388\/lpuupx"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2018.11.018"},{"key":"ref6","article-title":"NAND Flash Memory Characterization","author":"Heer","year":"2019"},{"key":"ref7","first-page":"2018","article-title":"3D NAND test structure and forming method thereof","author":"Lihong"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2021.3058697"},{"key":"ref9","article-title":"Testing system and method of NAND Flash based on MATLAB","author":"Sheng","year":"2018"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927029"},{"key":"ref11","article-title":"Resistance testing method for a 3D NAND memory bit line","author":"Guangmin","year":"2019"}],"event":{"name":"2024 IEEE 33rd Asian Test Symposium (ATS)","location":"Ahmedabad, India","start":{"date-parts":[[2024,12,17]]},"end":{"date-parts":[[2024,12,20]]}},"container-title":["2024 IEEE 33rd Asian Test Symposium (ATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10914681\/10915215\/10915226.pdf?arnumber=10915226","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T05:19:37Z","timestamp":1742015977000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10915226\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,17]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/ats64447.2024.10915226","relation":{},"subject":[],"published":{"date-parts":[[2024,12,17]]}}}