{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T11:17:41Z","timestamp":1762255061165,"version":"3.38.0"},"reference-count":36,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,12,17]]},"DOI":"10.1109\/ats64447.2024.10915272","type":"proceedings-article","created":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T17:45:02Z","timestamp":1741974302000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Fault Testing in AI-Accelerators: A Review"],"prefix":"10.1109","author":[{"given":"Bhargab B.","family":"Bhattacharya","sequence":"first","affiliation":[{"name":"Indian Statistical Institute,ACM Unit,Kolkata,India,700 108"}]},{"given":"Debesh K.","family":"Das","sequence":"additional","affiliation":[{"name":"Jadavpur University, India,Computer Science &amp; Engg., Dept.,Kolkata,India,700032"}]},{"given":"Subhajit","family":"Chatterjee","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Sc. and Tech.,School of VLSI Technology,Howrah,India,711 103"}]},{"given":"Hafizur","family":"Rahaman","sequence":"additional","affiliation":[{"name":"Indian Institute of Engineering Sc. and Tech.,School of VLSI Technology,Howrah,India,711 103"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.112130359"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3107401"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3048829"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3051841"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.eng.2020.01.007"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3236875"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.21144"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325250"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519770"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ITCIndia62949.2024.10652097"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3168782"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2017.2742698"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2024.3486658"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.807889"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2341674"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139171"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/NATW.2016.10"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2245376"},{"key":"ref20","article-title":"Identical core testing using dedicated compare and mask circuitry","volume-title":"U.S. Patent","author":"Whetsel","year":"2005"},{"key":"ref21","article-title":"Accelerating test pattern bring-up for rapid first silicon debug","volume-title":"Siemens Bus.","author":"Knowles","year":"2018"},{"key":"ref22","article-title":"AI chip DFT techniques for aggressive time-to-market","volume-title":"Siemens Bus.","author":"Singhal","year":"2019"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/92.365462"},{"article-title":"Gemmini: An agile systolic array generator enabling systematic evaluations of deep-learning architectures","year":"2019","author":"Genc","key":"ref24"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(89)90020-5"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1986.1270228"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700553"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ATS49688.2020.9301581"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3094741"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2019.2915656"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2018.8368656"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3102894"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9020338"},{"article-title":"Learning both weights and connections for efficient neural networks","year":"2015","author":"Han","key":"ref34"},{"article-title":"The state of sparsity in deep neural networks","year":"2019","author":"Gale","key":"ref35"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-018-04316-3"}],"event":{"name":"2024 IEEE 33rd Asian Test Symposium (ATS)","start":{"date-parts":[[2024,12,17]]},"location":"Ahmedabad, India","end":{"date-parts":[[2024,12,20]]}},"container-title":["2024 IEEE 33rd Asian Test Symposium (ATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10914681\/10915215\/10915272.pdf?arnumber=10915272","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T05:26:13Z","timestamp":1742016373000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10915272\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,17]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/ats64447.2024.10915272","relation":{},"subject":[],"published":{"date-parts":[[2024,12,17]]}}}