{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T04:14:21Z","timestamp":1742271261299,"version":"3.40.1"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002367","name":"Chinese Academy of Sciences","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,12,17]]},"DOI":"10.1109\/ats64447.2024.10915319","type":"proceedings-article","created":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T17:45:02Z","timestamp":1741974302000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction"],"prefix":"10.1109","author":[{"given":"Jiaping","family":"Tang","sequence":"first","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zizhen","family":"Liu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianan","family":"Mu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Feng","family":"Gu","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mingjun","family":"Wang","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenxing","family":"Li","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"Ye","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaowei","family":"Li","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"Chinese Academy of Sciences,State Key Lab of Processors, Institute of Computing Technology,Beijing,China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203886"},{"key":"ref2","first-page":"2","article-title":"SSIM: A Software Levelized Compiled-Code Simulator","volume-title":"24th ACM\/IEEE Design Automation Conference","author":"Wang"},{"key":"ref4","first-page":"180","article-title":"Khronos: Fusing Memory Access for Improved Hardware RTL Simulation","volume-title":"2023 56th IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Zhou"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185328"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.644038"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC50251.2020.00031"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2882903.2915220"},{"article-title":"Optimizing Cache Performance for Graph Analytics","year":"2016","author":"Zhang","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805857"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.536711"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114913"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00080"}],"event":{"name":"2024 IEEE 33rd Asian Test Symposium (ATS)","start":{"date-parts":[[2024,12,17]]},"location":"Ahmedabad, India","end":{"date-parts":[[2024,12,20]]}},"container-title":["2024 IEEE 33rd Asian Test Symposium (ATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10914681\/10915215\/10915319.pdf?arnumber=10915319","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T17:32:04Z","timestamp":1742232724000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10915319\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,17]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/ats64447.2024.10915319","relation":{},"subject":[],"published":{"date-parts":[[2024,12,17]]}}}