{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,14]],"date-time":"2026-07-14T02:24:45Z","timestamp":1783995885329,"version":"3.55.0"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,12,17]],"date-time":"2024-12-17T00:00:00Z","timestamp":1734393600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,12,17]]},"DOI":"10.1109\/ats64447.2024.10915452","type":"proceedings-article","created":{"date-parts":[[2025,3,14]],"date-time":"2025-03-14T17:45:02Z","timestamp":1741974302000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["LLM vs HLS for RTL Code Generation: Friend or Foe?"],"prefix":"10.1109","author":[{"given":"Sutirtha","family":"Bhattacharyya","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sutharshanan B","family":"G","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chandan","family":"Karfa","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Electronic Design Automation: Synthesis, Verification, and Test","author":"Wang","year":"2009"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2834439"},{"key":"ref3","volume-title":"VivadoHigh-LevelSynthesis"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3383347"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/lad62341.2024.10691721"},{"key":"ref6","article-title":"The dawn of ai-native eda: Opportunities and challenges of large circuit models","author":"Chen","year":"2024"},{"key":"ref7","article-title":"Llm4eda: Emerging progress in large language models for electronic design automation","author":"Zhong","year":"2023"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/asp-dac58780.2024.10473893"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI61997.2024.00130"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ITCIndia62949.2024.10651860"},{"key":"ref11","article-title":"Chipnemo: Domain-adapted llms for chip design","author":"Liu","year":"2023"},{"key":"ref12","volume-title":"C2hlsc: Can llms bridge the software-to-hardware design gap","author":"Collini","year":"2024"},{"key":"ref13","article-title":"Automated c\/c++ program repair for high-level synthesis via large language models","author":"Xu","year":"2024"},{"key":"ref14","doi-asserted-by":"crossref","DOI":"10.1109\/TCAD.2024.3483089","article-title":"Rtlcoder: Fully open-source and efficient llm-assisted rtl code generation technique","author":"Liu","year":"2024"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691683"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137086"},{"key":"ref17","first-page":"1","article-title":"Verigen: A large language model for verilog code generation","volume-title":"ACM TODAES","volume":"29","author":"Thakur","year":"2023"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DSD57027.2022.00019"},{"key":"ref20","article-title":"Chatgpt: A language model by openai","year":"2023"}],"event":{"name":"2024 IEEE 33rd Asian Test Symposium (ATS)","location":"Ahmedabad, India","start":{"date-parts":[[2024,12,17]]},"end":{"date-parts":[[2024,12,20]]}},"container-title":["2024 IEEE 33rd Asian Test Symposium (ATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10914681\/10915215\/10915452.pdf?arnumber=10915452","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,15]],"date-time":"2025-03-15T05:03:18Z","timestamp":1742014998000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10915452\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,12,17]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/ats64447.2024.10915452","relation":{},"subject":[],"published":{"date-parts":[[2024,12,17]]}}}