{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:15:04Z","timestamp":1761581704544,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/atsip.2018.8364454","type":"proceedings-article","created":{"date-parts":[[2018,5,24]],"date-time":"2018-05-24T18:46:02Z","timestamp":1527187562000},"page":"1-6","source":"Crossref","is-referenced-by-count":6,"title":["FFT implementation and optimization on FPGA"],"prefix":"10.1109","author":[{"given":"Tarek","family":"Belabed","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sabeur","family":"Jemmali","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chokri","family":"Souani","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSP.2014.6949921"},{"key":"ref11","first-page":"167","article-title":"Design and simulation of 32-point FFT using radix-2 algorithm for FPGA implementation","author":"haveliya","year":"2011","journal-title":"Adv Comput Commun Technol (ACCT) 2012 Second Int Conf"},{"key":"ref12","first-page":"514","article-title":"FPGA implementation of filtered image using 2D Gaussian filter","volume":"7","author":"sghaier","year":"2016","journal-title":"Int J Adv Comput Sci Appl"},{"key":"ref13","first-page":"122","article-title":"1024-Point pipeline FFT processor with pointer FIFOs based on FPGA","author":"zhong","year":"2011","journal-title":"2011 IEEE\/IFIP 19th Int Conf VLSI Syst VLSI-SoC 2011"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-415893-1.00004-4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008155020711"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1090\/S0025-5718-1965-0178586-1"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-65262-7"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CISP.2013.6745222"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-6629-0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126618300015"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MIM.2007.364962"},{"key":"ref9","first-page":"1","article-title":"A efficient design of a real-time FFT architecture based on FPGA","volume":"0","author":"yang","year":"2013","journal-title":"IET International Radar Conference 2013"}],"event":{"name":"2018 4th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP)","start":{"date-parts":[[2018,3,21]]},"location":"Sousse","end":{"date-parts":[[2018,3,24]]}},"container-title":["2018 4th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8360431\/8364333\/08364454.pdf?arnumber=8364454","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,6,11]],"date-time":"2018-06-11T19:07:30Z","timestamp":1528744050000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8364454\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/atsip.2018.8364454","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}