{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,15]],"date-time":"2026-04-15T19:11:03Z","timestamp":1776280263692,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/bcicts45179.2019.8972714","type":"proceedings-article","created":{"date-parts":[[2020,1,31]],"date-time":"2020-01-31T00:16:05Z","timestamp":1580429765000},"page":"1-6","source":"Crossref","is-referenced-by-count":4,"title":["Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges"],"prefix":"10.1109","author":[{"given":"Sebastien","family":"Blais","sequence":"first","affiliation":[{"name":"Ciena Corporation,Ottawa,Canada"}]},{"given":"Yuriy","family":"Greshishchev","sequence":"additional","affiliation":[{"name":"Ciena Corporation,Ottawa,Canada"}]},{"given":"Peter","family":"Schvan","sequence":"additional","affiliation":[{"name":"Ciena Corporation,Ottawa,Canada"}]},{"given":"Ian","family":"Betty","sequence":"additional","affiliation":[{"name":"Ciena Corporation,Ottawa,Canada"}]},{"given":"Douglas","family":"McGhan","sequence":"additional","affiliation":[{"name":"Ciena Corporation,Ottawa,Canada"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Basic DAC architectures I: string DACs and thermometer (fully decoded) DACs","author":"kester","year":"2008"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ECOC.2010.5621565"},{"key":"ref6","article-title":"Basic DAC architectures III: segmented DACs","author":"kester","year":"2008"},{"key":"ref5","article-title":"Basic DAC architectures II: binary DACs","author":"kester","year":"2008"},{"key":"ref8","first-page":"544","article-title":"A 24 GS\/s 6b ADC in 90 nm CMOS","author":"schvan","year":"2008","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref7","article-title":"A Linear Active Combiner Enabling an Interleaved 200GS\/s DAC with 44GHz Analog Bandwdith","year":"2017","journal-title":"BCTM Proceedings"},{"key":"ref2","article-title":"Beyond 100 Gb\/s: Capacity, Flexibility, and Network Optimization","author":"roberts","year":"2016","journal-title":"Invited J Opt Commun Netw"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SMIC.2007.322758"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2013.OTh1F.5"}],"event":{"name":"2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)","location":"Nashville, TN, USA","start":{"date-parts":[[2019,11,3]]},"end":{"date-parts":[[2019,11,6]]}},"container-title":["2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8961327\/8972708\/08972714.pdf?arnumber=8972714","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T19:22:29Z","timestamp":1756754549000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8972714\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/bcicts45179.2019.8972714","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}