{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T17:42:44Z","timestamp":1776447764463,"version":"3.51.2"},"reference-count":29,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,16]],"date-time":"2020-11-16T00:00:00Z","timestamp":1605484800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,16]],"date-time":"2020-11-16T00:00:00Z","timestamp":1605484800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,16]],"date-time":"2020-11-16T00:00:00Z","timestamp":1605484800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11,16]]},"DOI":"10.1109\/bcicts48439.2020.9392980","type":"proceedings-article","created":{"date-parts":[[2021,4,9]],"date-time":"2021-04-09T16:10:07Z","timestamp":1617984607000},"page":"1-8","source":"Crossref","is-referenced-by-count":18,"title":["Device Scaling roadmap and its implications for Logic and Analog platform"],"prefix":"10.1109","author":[{"given":"Alessio","family":"Spessot","sequence":"first","affiliation":[]},{"given":"Bertrand","family":"Parvais","sequence":"additional","affiliation":[]},{"given":"Amita","family":"Rawat","sequence":"additional","affiliation":[]},{"given":"Kenichi","family":"Miyaguchi","sequence":"additional","affiliation":[]},{"given":"Pieter","family":"Weckx","sequence":"additional","affiliation":[]},{"given":"Doyoung","family":"Jang","sequence":"additional","affiliation":[]},{"given":"Julien","family":"Ryckaert","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223656"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2017.8066651"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268430"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510618"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776513"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131494"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1117\/12.2011586"},{"key":"ref17","article-title":"Experimental Validation of Process InducedVariability Aware SPICE simulation platform","author":"rawat","year":"0","journal-title":"submitted to IEEE TED"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2018.8486857"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2017.7936356"},{"key":"ref28","article-title":"Advanced Transistors for High Frequency Applications (Invited)","volume":"97","author":"parvais","year":"2020","journal-title":"2020 ECS Trans"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614662"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075914"},{"key":"ref3","first-page":"112","author":"liebmann","year":"0","journal-title":"IEEE Symposium on VLSI Technology"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993631"},{"key":"ref29","author":"wang","year":"0","journal-title":"Power Amplifiers Performance Survey 2000-Present"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2017.2695455"},{"key":"ref8","article-title":"Buried power SRAM DTCO and system-level benchmarking in N3","author":"salahuddin","year":"2020","journal-title":"VLSI"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2018.8430415"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838497"},{"key":"ref9","first-page":"1","article-title":"Holisitic device exploration for 7 nm node","author":"raghavan","year":"0","journal-title":"Custom Integrated Circuits Conference (CICC) 2015 IEEE"},{"key":"ref1","first-page":"131","article-title":"A 22 nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors","author":"auth","year":"0","journal-title":"Symposium on VLSI Technology (VLSIT) 2012"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2878841"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510654"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993603"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.885649"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1587\/elex.11.20132011"},{"key":"ref26","article-title":"FinFET with Contact over Active-Gate for 5G Ultra-Wideband Applications","author":"razavieh","year":"0","journal-title":"Proc VLSI Symp"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998154"}],"event":{"name":"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","location":"Monterey, CA, USA","start":{"date-parts":[[2020,11,16]]},"end":{"date-parts":[[2020,11,19]]}},"container-title":["2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9392908\/9392902\/09392980.pdf?arnumber=9392980","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T11:36:11Z","timestamp":1656329771000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9392980\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,16]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/bcicts48439.2020.9392980","relation":{},"subject":[],"published":{"date-parts":[[2020,11,16]]}}}