{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T11:35:42Z","timestamp":1730201742574,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/cahpc.2018.8645930","type":"proceedings-article","created":{"date-parts":[[2019,2,21]],"date-time":"2019-02-21T18:19:26Z","timestamp":1550773166000},"page":"402-409","source":"Crossref","is-referenced-by-count":1,"title":["Design Space Exploration of Energy Efficient NoC-and Cache-Based Many-Core Architecture"],"prefix":"10.1109","author":[{"given":"Matheus A.","family":"Souza","sequence":"first","affiliation":[]},{"given":"Henrique C.","family":"Freitas","sequence":"additional","affiliation":[]},{"given":"Jean-Francois","family":"Mehaut","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416639"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2643669"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2017.8226033"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2017.8010167"},{"key":"ref14","first-page":"551","article-title":"Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big. LITTLE Architectures","author":"butko","year":"2015","journal-title":"IEEE Computer Society Annual Symposium on VLSI"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1007\/978-3-642-21292-5_3","article-title":"An approach for effective design space exploration","author":"kang","year":"2011","journal-title":"Foundations of Computer Software Modeling Development and Verification of Adaptive Systems"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3073763.3073770"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059093"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1177\/109434209100500306"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1016\/j.jpdc.2014.11.002","article-title":"On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms","volume":"76","author":"francesquini","year":"2015","journal-title":"J Parallel Distrib Comput"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670342"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1930037.1930044"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"490","DOI":"10.1109\/5.920580","article-title":"The future of wires","volume":"89","author":"ho","year":"2001","journal-title":"Proc of IEEE"},{"key":"ref1","first-page":"1","article-title":"Barriers to exascale computing","author":"simon","year":"2012","journal-title":"High Performance Computing for Computational Science"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2013.05.002"},{"key":"ref20","first-page":"1","article-title":"Evaluation of adaptive memory management techniques on the Tilera TILE-Gx platform","author":"fleig","year":"2014","journal-title":"Architecture of Computing Systems"},{"journal-title":"CACTI 6 0 A Tool to Model Large Caches","year":"2009","author":"muralimanohar","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2012.7476487"}],"event":{"name":"2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)","start":{"date-parts":[[2018,9,24]]},"location":"Lyon, France","end":{"date-parts":[[2018,9,27]]}},"container-title":["2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8638685\/8645847\/08645930.pdf?arnumber=8645930","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T02:40:31Z","timestamp":1643251231000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8645930\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/cahpc.2018.8645930","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}