{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T11:35:47Z","timestamp":1730201747170,"version":"3.28.0"},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,9]]},"DOI":"10.1109\/cahpc.2018.8645951","type":"proceedings-article","created":{"date-parts":[[2019,2,21]],"date-time":"2019-02-21T23:19:26Z","timestamp":1550791166000},"page":"17-24","source":"Crossref","is-referenced-by-count":7,"title":["From Java to FPGA: An Experience with the Intel HARP System"],"prefix":"10.1109","author":[{"given":"Pedro","family":"Caldeira","sequence":"first","affiliation":[]},{"given":"Jeronimo C.","family":"Penha","sequence":"additional","affiliation":[]},{"given":"Lucas","family":"Braganca","sequence":"additional","affiliation":[]},{"given":"Ricardo","family":"Ferreira","sequence":"additional","affiliation":[]},{"given":"Jose Augusto M.","family":"Nacif","sequence":"additional","affiliation":[]},{"given":"Renato","family":"Ferreira","sequence":"additional","affiliation":[]},{"given":"Fernando M. Q.","family":"Pereira","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2016.2537805"},{"journal-title":"Veriloggen A library for constructing a Verilog HDL source code in Python","year":"0","author":"takamaeda-yamazaki","key":"ref32"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"7:1","DOI":"10.1147\/JRD.2014.2380198","article-title":"Capi: A coherent accelerator processor interface","volume":"59","author":"stuecheli","year":"2015","journal-title":"IBM Journal of Research and Development"},{"key":"ref30","first-page":"173","article-title":"Scalable window generation for the intel broadwell+arria 10 and high-bandwidth FPGA systems","author":"greg","year":"2018","journal-title":"2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021727"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2016.117"},{"key":"ref35","first-page":"859","article-title":"OpenACC - first experiences with real-world applications","author":"sandra","year":"2012","journal-title":"Euro-Par"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1145\/2847263.2847269","article-title":"A study of pointer-chasing performance on shared-memory processor-FPGA systems","author":"weisz","year":"2016","journal-title":"Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays FPGA '16"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.61"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.3352"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-016-1108-7"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/jcc.21035"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.20"},{"key":"ref15","first-page":"11:1","article-title":"Creating high performance applications with intel's FPGA OpenCL&Trade; SDK","author":"ling","year":"2017","journal-title":"IWOCL"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0055237"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICSPC.2007.4728256"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2007.898281"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1145\/3174243.3174258","article-title":"A customizable matrix multiplication framework for the intel HARPv2 xeon+Fl'GA platform: A deep learning case study","author":"moss","year":"2018","journal-title":"2018 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"},{"key":"ref28","first-page":"176","article-title":"T. S. Accelerating k-means clustering on a tightly-coupled processor-fpga heterogeneous system","year":"2016","journal-title":"2016 IEEE 27th International Conference on Application-specific Systems Architectures and Processors (ASAP)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2017.8091025"},{"key":"ref27","first-page":"1","article-title":"Automatic parallelization of recursive functions with rewriting rules","volume":"x","author":"rocha","year":"2018","journal-title":"Science of Computer Programming"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.21"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1327452.1327492"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3035918.3035954"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2012.09.006"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1093\/bioinformatics\/13.6.609"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145704"},{"key":"ref2","first-page":"1","author":"caulfield","year":"2016","journal-title":"Microarchitecture (MICRO) 2016 49th Annual IEEE\/ACM International Symposium on IEEE"},{"journal-title":"Intel processors and FPGAs Better together","year":"0","author":"huffstetler","key":"ref9"},{"key":"ref1","first-page":"447","article-title":"ParallelME: A parallel mobile engine to explore heterogeneity in mobile computing architectures","author":"andrade","year":"2016","journal-title":"Euro-Par"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2018.02.004"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2011.4"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.41"},{"key":"ref24","doi-asserted-by":"crossref","first-page":"651","DOI":"10.1145\/2954679.2872415","article-title":"Generating configurable hardware from parallel patterns","volume":"51","author":"raghu","year":"2016","journal-title":"SIGPLAN Not"},{"key":"ref23","doi-asserted-by":"crossref","DOI":"10.5753\/wscad.2017.234","article-title":"Add - uma ferramenta de projeto de aceleradores com dataflow para alto desempenho","author":"penha","year":"2017","journal-title":"Simpósio em Sistemas Computacionais de Alto Desempenho (WSCAD)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.42"},{"key":"ref25","first-page":"136","article-title":"A generic parallel collection framework","author":"prokopec","year":"2011","journal-title":"Euro-Par"}],"event":{"name":"2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)","start":{"date-parts":[[2018,9,24]]},"location":"Lyon, France","end":{"date-parts":[[2018,9,27]]}},"container-title":["2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8638685\/8645847\/08645951.pdf?arnumber=8645951","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,27]],"date-time":"2022-01-27T07:43:20Z","timestamp":1643269400000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8645951\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,9]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/cahpc.2018.8645951","relation":{},"subject":[],"published":{"date-parts":[[2018,9]]}}}