{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T14:28:57Z","timestamp":1768314537170,"version":"3.49.0"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,11,25]],"date-time":"2025-11-25T00:00:00Z","timestamp":1764028800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,11,25]],"date-time":"2025-11-25T00:00:00Z","timestamp":1764028800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,11,25]]},"DOI":"10.1109\/candarw68385.2025.00074","type":"proceedings-article","created":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T18:20:34Z","timestamp":1768242034000},"page":"377-379","source":"Crossref","is-referenced-by-count":0,"title":["Exploring Shared Reservation Stations for Embedded Processors"],"prefix":"10.1109","author":[{"given":"Kazuki","family":"Kogure","sequence":"first","affiliation":[{"name":"Keio University Kouhoku-ku, 223-8852,Graduate School of Science and Technology,Yokohama-shi,Kanagawa,Japan"}]},{"given":"Nobuyuki","family":"Yamasaki","sequence":"additional","affiliation":[{"name":"Keio University Kouhoku-ku, 223-8852,Graduate School of Science and Technology,Yokohama-shi,Kanagawa,Japan"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2022.3164338"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00042"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00023"},{"key":"ref4","article-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy","year":"2021","journal-title":"Sixth Edition"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IWIAS.2006.36"},{"key":"ref6","article-title":"AMD Virtex UltraScale+ HBM VCU128 FPGA Evaluation Kit"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"}],"event":{"name":"2025 Thirteenth International Symposium on Computing and Networking Workshops (CANDARW)","location":"Yamagata, Japan","start":{"date-parts":[[2025,11,25]]},"end":{"date-parts":[[2025,11,28]]}},"container-title":["2025 Thirteenth International Symposium on Computing and Networking Workshops (CANDARW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11318850\/11318884\/11318900.pdf?arnumber=11318900","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,13]],"date-time":"2026-01-13T09:15:04Z","timestamp":1768295704000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11318900\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,25]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/candarw68385.2025.00074","relation":{},"subject":[],"published":{"date-parts":[[2025,11,25]]}}}