{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T15:45:05Z","timestamp":1773330305183,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/cases.2013.6662515","type":"proceedings-article","created":{"date-parts":[[2013,11,27]],"date-time":"2013-11-27T21:53:08Z","timestamp":1385589188000},"page":"1-10","source":"Crossref","is-referenced-by-count":25,"title":["Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies"],"prefix":"10.1109","author":[{"given":"Fazal","family":"Hameed","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lars","family":"Bauer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jorg","family":"Henkel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601880"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.52"},{"key":"14","first-page":"128","article-title":"Memory access scheduling","author":"rixner","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919638"},{"key":"12","article-title":"Fundamental latency trade-offs in architecting DRAM caches","author":"qureshi","year":"2012","journal-title":"Proc 40th Ann IEEE\/ACM Symp Microarchitecture (MICRO)"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2011.2131610"},{"key":"1","year":"0","journal-title":"Standard Performance Evaluation Corporation"},{"key":"10","article-title":"Supporting very large DRAM caches with compound access scheduling and miss-maps","author":"loh","year":"2012","journal-title":"IEEE Micro Magazine Special Issue on Top Picks in Computer Architecture Conferences"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.51"},{"key":"6","article-title":"Simpoint 3.0: Faster and more flexible program analysis","volume":"7","author":"hamerly","year":"2005","journal-title":"Journal of Instruction Level Parallelism"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.030"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369763"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669139"}],"event":{"name":"2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","location":"Montreal, QC, Canada","start":{"date-parts":[[2013,9,29]]},"end":{"date-parts":[[2013,10,4]]}},"container-title":["2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6648478\/6662498\/06662515.pdf?arnumber=6662515","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T02:42:17Z","timestamp":1490236937000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6662515\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/cases.2013.6662515","relation":{},"subject":[],"published":{"date-parts":[[2013,9]]}}}