{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T00:13:17Z","timestamp":1787011997580,"version":"3.56.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/cases.2015.7324552","type":"proceedings-article","created":{"date-parts":[[2015,11,12]],"date-time":"2015-11-12T18:05:25Z","timestamp":1447351525000},"page":"117-126","source":"Crossref","is-referenced-by-count":6,"title":["Saving memory movements through vector processing in the DRAM"],"prefix":"10.1109","author":[{"given":"Marco A. Z.","family":"Alves","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paulo C.","family":"Santos","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Francis B.","family":"Moreira","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matthias","family":"Diener","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luigi","family":"Carro","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Drama: An architecture for accelerated processing near memory","author":"farmahini-farahani","year":"2014","journal-title":"Computer Architecture Letters"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/13310.13312"},{"key":"ref12","year":"2012","journal-title":"Intel Intel &#x00AE; Xeon Phi TM Coprocessor Instruction Set Architecture Reference Manual"},{"key":"ref13","article-title":"Intel. Intel Atom Processor E3800 Product Family","year":"2015","journal-title":"Technical Report"},{"key":"ref14","author":"jacob","year":"2008","journal-title":"Memory Systems Cache DRAM Disk"},{"key":"ref15","article-title":"Tiered-latency dram: A low latency and low cost dram architecture","author":"lee","year":"0","journal-title":"Int Symp on High Performance Computer Architecture (HPCA) 2013"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155673"},{"key":"ref17","article-title":"Micron. 1gb: x4, x8, x16 ddr3 sdram features","year":"2006","journal-title":"1Gb_DDR3_SDRAM pdf - Rev"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796763"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/40.592312"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2013.6670336"},{"key":"ref4","year":"2010","journal-title":"Cortex-A9 Technical Reference Manual"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702348"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC-CSS-ICESS.2015.166"},{"key":"ref6","article-title":"Evaluation of existing architectures in iram systems","author":"bowman","year":"0","journal-title":"Workshop on Mixing Logic and DRAM 1997"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1317","DOI":"10.7873\/DATE.2015.0054","article-title":"High Performance AXI-4.0 Based Interconnect for Extensible Smart Memory Cubes","author":"erfan azarkhish","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514197"},{"key":"ref7","author":"davis","year":"2001","journal-title":"Modern Dram Architectures"},{"key":"ref2","author":"alves","year":"2014","journal-title":"Increasing Energy Efficiency of Processor Caches Via Line Usage Predictors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/54.748803"},{"key":"ref1","author":"adkisson","year":"2002","journal-title":"Embedded dram on silicon-on-insulator substrate"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2014.54"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232984"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844483"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/216585.216588"},{"key":"ref23","article-title":"A near-memory processor for vector, streaming and bit manipulation workloads","author":"wei","year":"2005","journal-title":"Technical Report UIUC DCS-R-2005-2557 University of Illinois at Urbana-Champaign Dept of Computer Science"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/40.946676"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2492408.2492418"}],"event":{"name":"2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","location":"Amsterdam, Netherlands","start":{"date-parts":[[2015,10,4]]},"end":{"date-parts":[[2015,10,9]]}},"container-title":["2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7313573\/7324531\/07324552.pdf?arnumber=7324552","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T09:51:39Z","timestamp":1567331499000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7324552\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/cases.2015.7324552","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}