{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T23:13:16Z","timestamp":1725405196714},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/ccece.2014.6900947","type":"proceedings-article","created":{"date-parts":[[2014,9,26]],"date-time":"2014-09-26T15:29:34Z","timestamp":1411745374000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["10 GHz throughput FinFET dual-edge triggered flip-flops"],"prefix":"10.1109","author":[{"given":"S. E.","family":"Esmaeili","sequence":"first","affiliation":[]},{"given":"A. J.","family":"Al-Khalili","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"17","DOI":"10.1109\/ICECS.2012.6463565"},{"year":"0","key":"18"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1049\/iet-cdt.2010.0005"},{"doi-asserted-by":"publisher","key":"16","DOI":"10.1109\/TVLSI.2005.844302"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/ECCTD.2009.5275131"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1109\/ISCAS.2007.378255"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/TVLSI.2005.844302"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/ICCD.2001.955087"},{"key":"3","first-page":"348","article-title":"Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduce power consumption","author":"tawfik","year":"2008","journal-title":"IEEE Asia Pacific Conference on Circuits and Systems"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1145\/1146909.1147047"},{"key":"1","first-page":"251","article-title":"FinFET scaling at 10nm gate length","author":"chang","year":"2002","journal-title":"International Electron Device Meeting"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/JPROC.2002.808156"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1145\/871506.871524"},{"key":"6","first-page":"399","article-title":"A low power symmetrically pulsed dual edge-triggered flip-flop","author":"nedovic","year":"2002","journal-title":"Proceedings of the 28th European Solid-State Circuits Conference"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/TC.2005.91"},{"key":"4","first-page":"4329","article-title":"Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop","author":"liu","year":"2006","journal-title":"IEEE International Symposium on Circuits and Systems"},{"key":"9","first-page":"1","article-title":"Clock distribution networks in 3-D integrated systems","author":"pavlidis","year":"2010","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ISSCC.2000.839705"}],"event":{"name":"2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE)","start":{"date-parts":[[2014,5,4]]},"location":"Toronto, ON, Canada","end":{"date-parts":[[2014,5,7]]}},"container-title":["2014 IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6893068\/6900900\/06900947.pdf?arnumber=6900947","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T17:58:35Z","timestamp":1490291915000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6900947\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/ccece.2014.6900947","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}