{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T07:32:16Z","timestamp":1725694336466},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/ccece.2017.7946666","type":"proceedings-article","created":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T21:25:48Z","timestamp":1497993948000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["An efficient optimal clock network buffer sizing with slew consideration"],"prefix":"10.1109","author":[{"given":"Ali","family":"Farshidi","sequence":"first","affiliation":[]},{"given":"Logan","family":"Rakai","sequence":"additional","affiliation":[]},{"given":"Laleh","family":"Behjat","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996614"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2293067"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547521"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.5120\/16737-7023"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419835"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2007.900837"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/43.602470"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2007.4511123"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2066030"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1999.777319"},{"journal-title":"International Symposium on Physical Design (ISPD) 2010 clock network synthesis contest ACM","year":"0","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1992.270316"},{"journal-title":"International Symposium on Physical Design (ISPD) 2009 clock network synthesis contest ACM","year":"0","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019088"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2144595"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/81.296331"},{"key":"ref8","first-page":"1","article-title":"Cmcs: Current-mode clock synthesis","author":"islam","year":"2016","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref7","first-page":"1","article-title":"A multi-objective co-optimization of buffer and wire sizes in high performance clock trees","author":"farshidi","year":"2016","journal-title":"IEEE Transactions on Circuits and Systems II Express Briefs"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2013.6863954"},{"key":"ref9","first-page":"484","article-title":"Synthesis of resonant clock networks supporting dynamic voltage \/ frequency scaling","author":"ahn","year":"2015","journal-title":"Asia and South Pacific Design Automation Conference"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2002.146739"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744776"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/43.205004"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419833"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.830932"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227749"},{"journal-title":"ngspice 24","year":"0","key":"ref26"},{"journal-title":"Mosek 6 0","year":"0","key":"ref25"}],"event":{"name":"2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)","start":{"date-parts":[[2017,4,30]]},"location":"Windsor, ON","end":{"date-parts":[[2017,5,3]]}},"container-title":["2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7938141\/7946583\/07946666.pdf?arnumber=7946666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,3]],"date-time":"2018-05-03T21:22:28Z","timestamp":1525382548000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7946666\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/ccece.2017.7946666","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}