{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T12:07:25Z","timestamp":1730203645122,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,12]],"date-time":"2021-09-12T00:00:00Z","timestamp":1631404800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,12]],"date-time":"2021-09-12T00:00:00Z","timestamp":1631404800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,12]]},"DOI":"10.1109\/ccece53047.2021.9569176","type":"proceedings-article","created":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T21:13:38Z","timestamp":1635282818000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Implementing Multistage Interconnection Networks on FPGA Using Chisel Language"],"prefix":"10.1109","author":[{"given":"Andy","family":"Gallay","sequence":"first","affiliation":[{"name":"Polytechnique Montréal,MOTCE Laboratory,Department of Computer Engineering,Montreal,PQ,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tarek","family":"Ould-Bachir","sequence":"additional","affiliation":[{"name":"Polytechnique Montréal,MOTCE Laboratory,Department of Computer Engineering,Montreal,PQ,Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810667"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203780"},{"key":"ref13","article-title":"Specification for the firrtl language","author":"li","year":"2016","journal-title":"EECS Department University of California Berkeley Tech Rep UCB\/EECS-2016–9"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1983.1676295"},{"key":"ref4","article-title":"Digital Design with Chisel","author":"schoeberl","year":"2019","journal-title":"Kindle Direct Publishing"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref6","first-page":"93","article-title":"LDPC decoder based on Chisel","author":"wu","year":"0","journal-title":"2020 IEEE 3rd International Conference on Electronics and Communication Engineering (ICECE)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSC.2018.8585292"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"694","DOI":"10.1109\/TC.1980.1675651","article-title":"On a class of multistage interconnection networks","volume":"c 29","author":"wu","year":"1980","journal-title":"IEEE Transactions on Computers"},{"journal-title":"MIN implementation using VHDL and Chisel","year":"2021","author":"gallay","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref1","first-page":"23","article-title":"High-level synthesis","author":"jo\u00e3o","year":"2016","journal-title":"FPGAs for Software Programmers"},{"key":"ref9","first-page":"1","article-title":"A low-latency reconfigurable multistage interconnection network","author":"monta\u00f1o","year":"0","journal-title":"IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)"}],"event":{"name":"2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","start":{"date-parts":[[2021,9,12]]},"location":"ON, Canada","end":{"date-parts":[[2021,9,17]]}},"container-title":["2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9569025\/9569028\/09569176.pdf?arnumber=9569176","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T00:10:49Z","timestamp":1659485449000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9569176\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/ccece53047.2021.9569176","relation":{},"subject":[],"published":{"date-parts":[[2021,9,12]]}}}