{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T06:25:34Z","timestamp":1771309534850,"version":"3.50.1"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,8]],"date-time":"2025-10-08T00:00:00Z","timestamp":1759881600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,8]],"date-time":"2025-10-08T00:00:00Z","timestamp":1759881600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,8]]},"DOI":"10.1109\/ccmcc67628.2025.11380528","type":"proceedings-article","created":{"date-parts":[[2026,2,16]],"date-time":"2026-02-16T21:03:11Z","timestamp":1771275791000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Design Space Exploration of a Direct Cached Memory Access Controller Optimized for HBM Memory Systems using TAPRE-HBM"],"prefix":"10.1109","author":[{"given":"Gia Bao","family":"Thieu","sequence":"first","affiliation":[{"name":"Technische Universit&#x00E4;t Braunschweig,Chair for Chip Design for Embedded Computing,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johannes","family":"Kn\u00f6dtel","sequence":"additional","affiliation":[{"name":"University of Rostock,Institute of Applied Microelectronics and Computer Engineering,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Florian","family":"Rokohl","sequence":"additional","affiliation":[{"name":"University of Rostock,Institute of Applied Microelectronics and Computer Engineering,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[{"name":"University of Rostock,Institute of Applied Microelectronics and Computer Engineering,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guillermo","family":"Pay\u00e1-Vay\u00e1","sequence":"additional","affiliation":[{"name":"Technische Universit&#x00E4;t Braunschweig,Chair for Chip Design for Embedded Computing,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"issue":"2","key":"ref1","first-page":"151","article-title":"A Survey of Different Approaches for Overcoming the Processor - Memory Bottleneck","volume-title":"International Journal of Computer Science and Information Technology","volume":"9","author":"Efnusheva","year":"2017"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/IMW.2017.7939084","article-title":"HBM (High Bandwidth Memory) DRAM Technology and Architecture","volume-title":"2017 IEEE International Memory Workshop (IMW)","author":"Jun","year":"2017"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-40843-4_30"},{"key":"ref4","first-page":"1","article-title":"ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving","volume-title":"2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)","author":"Thieu"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3730582"},{"key":"ref6","article-title":"The gem5 Simulator: Version 20.0+","author":"Lowe-Power","year":"2020"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-022-00727-4"},{"key":"ref8","article-title":"Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator","author":"Luo","year":"2023"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-42921-7_21"},{"key":"ref10","article-title":"HBM Configuration and Use \u2022 Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) \u2022 Reader \u2022 AMD Technical Information Portal"},{"key":"ref11","first-page":"1","article-title":"High Bandwidth Memory on FPGAs: A Data Analytics Perspective","volume-title":"2020 30th International Conference on Field-Programmable Logic and Applications (FPL)","author":"Kara"},{"key":"ref12","first-page":"152","article-title":"Fast HBM Access with FPGAs: Analysis, Architectures, and Applications","volume-title":"2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","author":"Holzinger"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3547658"},{"issue":"2","key":"ref14","first-page":"404","article-title":"TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBMBased FPGAs","volume-title":"IEEE Transactions on Emerging Topics in Computing","volume":"11","author":"Qiao","year":"2023"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3650037"},{"key":"ref16","first-page":"9","article-title":"NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling","volume-title":"2020 30th International Conference on Field-Programmable Logic and Applications (FPL)","author":"Singh"},{"key":"ref17","first-page":"1","article-title":"GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs","volume-title":"2021 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","author":"Hu"},{"key":"ref18","first-page":"148","article-title":"A High Throughput Parallel Hash Table Accelerator on HBM-enabled FPGAs","volume-title":"2020 International Conference on Field-Programmable Technology (ICFPT)","author":"Yang"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-44534-8_23"},{"key":"ref20","doi-asserted-by":"crossref","DOI":"10.1145\/3579371.3589350","article-title":"Tpu v4: An optically reconfigurable supercomputer for machine learning with hardware support for embeddings","author":"Jouppi","year":"2023"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-15074-6_3"},{"key":"ref22","article-title":"Nvidia ampere architecture whitepaper","volume-title":"NVIDIA Corporation, Tech. Rep.","year":"2020"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-00454-4_17"},{"key":"ref24","article-title":"Portable and Scalable FPGA Emulation of a Massive-Parallel Vector Processor","volume-title":"31st European Conference on Parallel and Distributed Processing (Euro-Par)","author":"Thieu"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HICSS.1995.375383"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE-Berlin58801.2023.10375652"},{"key":"ref27","article-title":"Inverted residuals and linear bottlenecks: Mobile networks for classification, detection and segmentation","volume-title":"CoRR","author":"Sandler","year":"2018"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2018.8621865"}],"event":{"name":"2025 Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC)","location":"Dresden, Germany","start":{"date-parts":[[2025,10,8]]},"end":{"date-parts":[[2025,10,10]]}},"container-title":["2025 Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11380186\/11380408\/11380528.pdf?arnumber=11380528","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,17]],"date-time":"2026-02-17T05:57:00Z","timestamp":1771307820000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11380528\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,8]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/ccmcc67628.2025.11380528","relation":{},"subject":[],"published":{"date-parts":[[2025,10,8]]}}}