{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:38:42Z","timestamp":1729676322395,"version":"3.28.0"},"reference-count":26,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cgo.2003.1191541","type":"proceedings-article","created":{"date-parts":[[2003,12,22]],"date-time":"2003-12-22T17:34:10Z","timestamp":1072114450000},"page":"149-158","source":"Crossref","is-referenced-by-count":4,"title":["Improving quasi-dynamic schedules through region slip"],"prefix":"10.1109","author":[{"given":"F.","family":"Spadini","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Fahs","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Patel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.S.","family":"Lumetta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1007\/978-1-4615-3200-2_7"},{"year":"2000","journal-title":"Intel IA-64 Architecture Software Developer's Manual","key":"ref11"},{"key":"ref12","article-title":"The technology behind Crusoe processors","author":"klaiber","year":"2000","journal-title":"Technical Report"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/MICRO.1992.696999"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1007\/BF02577867"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/ISCA.1999.765946"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/HPCA.2001.903249"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/ISCA.1997.604516"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/PACT.1998.727183"},{"key":"ref19","article-title":"Weld: A multithreading technique towards latency-tolerant VLIW processors","author":"ozer","year":"2001","journal-title":"International Conference of High-Performance Computing"},{"key":"ref4","article-title":"Dynamically Scheduling VLIW Instructions","volume":"60","author":"desouza","year":"2000","journal-title":"Journal of Parallel and Distributed Computing"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/123465.123471"},{"key":"ref6","article-title":"Performance Characterization of a Hardware Framework for Dynamic Optimization","author":"fahs","year":"2001","journal-title":"Proceedings of the 34th Annual International Symposium on Microarchitecture"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1145\/384286.264126","article-title":"Daisy: Dynamic compilation for 100% architectural compatibility","author":"ebcio?lu","year":"1997","journal-title":"Proceedings of the 24th Annual International Symposium on Computer Architecture"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/12276.13312"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TC.1981.1675827"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/377792.377854"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1023\/A:1018702632204"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1145\/335231.335263"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/ISCA.1997.604689"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1145\/360128.360160","article-title":"Increasing the size of atomic instruction blocks using control flow assertions","author":"patel","year":"2000","journal-title":"Proceedings of the 33th Annual International Symposium on Microarchitecture"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/12.931895"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/HPCA.2003.1183535"},{"key":"ref23","first-page":"2","article-title":"Boa: Targeting multigigahertz with binary translation","author":"sathaye","year":"1999","journal-title":"IEEE TCCA Newsletter"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/2.825695"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/TC.1984.1676375"}],"event":{"acronym":"CGO-03","name":"International Symposium on Code Generation and Optimization. CGO 2003","location":"San Francisco, CA, USA"},"container-title":["International Symposium on Code Generation and Optimization, 2003. CGO 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8475\/26704\/01191541.pdf?arnumber=1191541","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,13]],"date-time":"2021-06-13T16:30:05Z","timestamp":1623601805000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1191541\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/cgo.2003.1191541","relation":{},"subject":[]}}