{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,25]],"date-time":"2026-10-25T18:13:32Z","timestamp":1792952012814,"version":"4.5.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cgo.2004.1281673","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T10:19:45Z","timestamp":1086862785000},"page":"175-186","source":"Crossref","is-referenced-by-count":4,"title":["Code generation for single-dimension software pipelining of multi-dimensional loops"],"prefix":"10.1109","author":[{"family":"Hongbo Rong","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"A.","family":"Douillet","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"R.","family":"Govindarajan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"G.R.","family":"Gao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Intel IA-64 Architecture Software Developer\u2019s Manual, Vol. 1: IA-64 Application Architecture","year":"2001"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/212094.212131"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205184"},{"key":"ref4","first-page":"29","article-title":"Controlling code size of software-pipelined loops on the TMS320C6000 VLIW DSP architecture","volume-title":"Proceedings of 3rd IEEE\/ACM Workshop on Media and Stream Processors","author":"Granston"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/155090.155115"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/53990.54022"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176242"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45306-7_12"},{"key":"ref9","article-title":"Livermore loops coded in c","author":"Peters"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/BF01205181"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697012"},{"key":"ref12","article-title":"Software Pipelining of Nested Loops","author":"Rong","year":"2001"},{"key":"ref13","article-title":"Hardware controlled shifts and rotations supporting software pipelining of loop nests","volume-title":"China Patent","author":"Rong","year":"2000"},{"key":"ref14","article-title":"Single-dimension software-pipelining for multi-dimensional loops","volume-title":"Proceedings of the 2004 International Symposium on Code Generation and Optimization (CGO)","author":"Rong"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-61053-7_49"}],"event":{"name":"International Symposium on Code Generation and Optimization, 2004. CGO 2004.","location":"San Jose, CA, USA"},"container-title":["International Symposium on Code Generation and Optimization, 2004. CGO 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9012\/28612\/01281673.pdf?arnumber=1281673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,10,24]],"date-time":"2026-10-24T05:50:14Z","timestamp":1792821014000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1281673\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/cgo.2004.1281673","relation":{},"subject":[]}}