{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,11]],"date-time":"2026-07-11T16:42:48Z","timestamp":1783788168852,"version":"3.55.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/cgo.2019.8661186","type":"proceedings-article","created":{"date-parts":[[2019,3,8]],"date-time":"2019-03-08T00:01:46Z","timestamp":1552003306000},"page":"229-241","source":"Crossref","is-referenced-by-count":14,"title":["Decoding CUDA Binary"],"prefix":"10.1109","author":[{"given":"Ari B.","family":"Hayes","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fei","family":"Hua","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jin","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yanhao","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eddy Z.","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"209","article-title":"Gpu taint tracking","author":"hayes","year":"2017","journal-title":"USENIX ATC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref12","first-page":"1273","article-title":"Critical points based register-concurrency autotuning for gpus","author":"li","year":"2016","journal-title":"Proceedings of the 2016 Conference on Design Automation & Test in Europe"},{"key":"ref13","author":"hayes","year":"2019","journal-title":"Decoding cuda binary - opcodes"},{"key":"ref14","author":"hayes","year":"2019","journal-title":"Decoding cuda binary - decoded instructions"},{"key":"ref15","author":"hayes","year":"2019","journal-title":"Decoding cuda binary - file format"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452013"},{"key":"ref17","author":"hou","year":"2012","journal-title":"Asfermi An Assembler for the NVIDIA Fermi Instruction Set"},{"key":"ref18","article-title":"Dissecting the nvidia volta gpu architecture via microbenchmarking","author":"jia","year":"2018","journal-title":"arXiv preprint arXiv 1804 02671"},{"key":"ref19","year":"0","journal-title":"GPU Computing SDK"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3018743.3018755"},{"key":"ref3","author":"gray","year":"2014","journal-title":"MaxAs Assembler for Nvidia Maxwell Architecture"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2597652.2597685"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2015.7108420"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2751205.2751232"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2988336.2988355"},{"key":"ref2","article-title":"maxdnn: an efficient convolution kernel for deep learning with maxwell gpus","author":"lavin","year":"2015","journal-title":"arXiv preprint arXiv 1501 06633"},{"key":"ref1","first-page":"1","article-title":"Performance upper bound analysis and optimization of sgemm on fermi and kepler gpus","author":"lai","year":"2013","journal-title":"IEEE Computer Society"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2014.115"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref22","author":"paxson","year":"1995","journal-title":"Flex–fast lexical analyzer generator"},{"key":"ref21","author":"hayes","year":"2019","journal-title":"Decoding cuda binary - special registers"},{"key":"ref24","author":"hayes","year":"2019","journal-title":"Decoding cuda binary artifact"},{"key":"ref23","author":"donnelly","year":"2000","journal-title":"Bison The Yacc-compatible Parser Generator"}],"event":{"name":"2019 IEEE\/ACM International Symposium on Code Generation and Optimization (CGO)","location":"Washington, DC, USA","start":{"date-parts":[[2019,2,16]]},"end":{"date-parts":[[2019,2,20]]}},"container-title":["2019 IEEE\/ACM International Symposium on Code Generation and Optimization (CGO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8653576\/8661160\/08661186.pdf?arnumber=8661186","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:17:40Z","timestamp":1658261860000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8661186\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/cgo.2019.8661186","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}