{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:05:27Z","timestamp":1740099927263,"version":"3.37.3"},"reference-count":64,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,2,27]],"date-time":"2021-02-27T00:00:00Z","timestamp":1614384000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,2,27]],"date-time":"2021-02-27T00:00:00Z","timestamp":1614384000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,27]],"date-time":"2021-02-27T00:00:00Z","timestamp":1614384000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100010418","name":"Institute of Information and Communication Technology Planning and Evaluation (IITP)","doi-asserted-by":"publisher","award":["IITP-2018-0-01392,IITP-2020-0-01847"],"award-info":[{"award-number":["IITP-2018-0-01392,IITP-2020-0-01847"]}],"id":[{"id":"10.13039\/501100010418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,27]]},"DOI":"10.1109\/cgo51591.2021.9370341","type":"proceedings-article","created":{"date-parts":[[2021,3,11]],"date-time":"2021-03-11T21:33:26Z","timestamp":1615498406000},"page":"327-339","source":"Crossref","is-referenced-by-count":0,"title":["Thread-Aware Area-Efficient High-Level Synthesis Compiler for Embedded Devices"],"prefix":"10.1109","author":[{"given":"Changsu","family":"Kim","sequence":"first","affiliation":[{"name":"POSTECH,Pohang,Republic of Korea"}]},{"given":"Shinnung","family":"Jeong","sequence":"additional","affiliation":[{"name":"Yonsei University,Seoul,Republic of Korea"}]},{"given":"Sungjun","family":"Cho","sequence":"additional","affiliation":[{"name":"POSTECH,Pohang,Republic of Korea"}]},{"given":"Yongwoo","family":"Lee","sequence":"additional","affiliation":[{"name":"Yonsei University,Seoul,Republic of Korea"}]},{"given":"William","family":"Song","sequence":"additional","affiliation":[{"name":"Yonsei University,Seoul,Republic of Korea"}]},{"given":"Youngsok","family":"Kim","sequence":"additional","affiliation":[{"name":"Yonsei University,Seoul,Republic of Korea"}]},{"given":"Hanjun","family":"Kim","sequence":"additional","affiliation":[{"name":"Yonsei University,Seoul,Republic of Korea"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927432"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ETFA.2005.1612697"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718365"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2016.34"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/512529.512550"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2000.862383"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.36"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2006.40"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2015.7293958"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2015.7393142"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270297"},{"journal-title":"SDAccel development environment","year":"2020","key":"ref62"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289841"},{"journal-title":"SDSoC Development Environment","year":"2018","key":"ref63"},{"key":"ref28","first-page":"270","article-title":"Streamroller:: Automatic synthesis of prescribed throughput accelerator pipelines","author":"mahlke","year":"0","journal-title":"Proceedings of the 4th international conference on Hardware\/software codesign and system synthesis (CODES+ISSS '06) CODESISSS"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2720623"},{"key":"ref27","first-page":"1355","volume":"20","author":"mahlke","year":"0","journal-title":"Bitwidth cognizant architecture synthesis of custom hardware accelerators"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1542452.1542456"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2018.2827388"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3025453.3025773"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2017.7863740"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2006.10"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281675"},{"key":"ref24","first-page":"12","article-title":"Cost sensitive modulo scheduling in a loop accelerator synthesis system","author":"fan","year":"0","journal-title":"38th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CAHPC.2018.8645951"},{"journal-title":"MKPipe A Compiler Framework for Optimizing Multi-Kernel Workloads in OpenCL for FPGA","year":"0","author":"liu","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629987"},{"journal-title":"Raspbian Operating System","year":"2020","key":"ref50"},{"journal-title":"Arduino FreeRTOS Library","year":"2020","key":"ref51"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2117-1"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145712"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484821"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344688"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382681"},{"key":"ref54","first-page":"702","article-title":"High-level synthesis challenges and solutions for a dynamically reconfigurable processor","author":"toi","year":"2006","journal-title":"IEEE\/ACM International Conference on Computer Aided Design ser ICCAD '06"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147059"},{"journal-title":"Arduino Thread","year":"2020","key":"ref52"},{"journal-title":"Bluespec Inc","year":"2020","key":"ref10"},{"journal-title":"Catapult High-Level Synthesis","year":"2020","key":"ref11"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ReCoSoC.2013.6581538"},{"journal-title":"CyberWorkBench","year":"2020","key":"ref12"},{"journal-title":"ImpulseC accelerated technologies","year":"2020","key":"ref13"},{"journal-title":"Vivado High-Level Synthesis","year":"2020","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2110592"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339221"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645550"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2010.28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SENSORCOMM.2009.23"},{"key":"ref3","first-page":"1","article-title":"Multi-sensor system for remote environmental (air and water) quality monitoring","author":"simic","year":"2016","journal-title":"2016 24th Telecommun Forum (TELFOR)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1644038.1644052"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2378256"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s11036-005-1567-8"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"journal-title":"Altera SDK for OpenCL","year":"2020","key":"ref9"},{"key":"ref46","doi-asserted-by":"crossref","first-page":"433","DOI":"10.1145\/1146909.1147025","article-title":"An efficient and versatile scheduling algorithm based on sdc formulation","author":"cong","year":"2006","journal-title":"2006 43rd ACM\/IEEE Design Automation Conference"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/1250734.1250767"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123350"},{"journal-title":"Duro High-Level Synthesis Compiler","year":"2020","key":"ref42"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311336"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.83"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2513673"}],"event":{"name":"2021 IEEE\/ACM International Symposium on Code Generation and Optimization (CGO)","start":{"date-parts":[[2021,2,27]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2021,3,3]]}},"container-title":["2021 IEEE\/ACM International Symposium on Code Generation and Optimization (CGO)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9370300\/9370301\/09370341.pdf?arnumber=9370341","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T15:42:21Z","timestamp":1652197341000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9370341\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,27]]},"references-count":64,"URL":"https:\/\/doi.org\/10.1109\/cgo51591.2021.9370341","relation":{},"subject":[],"published":{"date-parts":[[2021,2,27]]}}}