{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T17:01:02Z","timestamp":1725555662642},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2002.1012768","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T21:52:33Z","timestamp":1056577953000},"page":"67-70","source":"Crossref","is-referenced-by-count":0,"title":["The architecture of dual-mode FPGA embedded system blocks"],"prefix":"10.1109","author":[{"given":"E.","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.J.E.","family":"Wilton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1998.694978"},{"key":"ref11","article-title":"SIS: A System for Sequential Circuit Analysis","author":"sentovich","year":"1992","journal-title":"Tech Rep UCB\/ERL M92\/41"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/123186.123418"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275138"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1109\/FPGA.1995.242047","article-title":"SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays","author":"wilton","year":"1995","journal-title":"Proceedings of the ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44687-7_6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296415"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1992.591108"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/54.765206"},{"journal-title":"Programmable Logic Device Family Datasheet","year":"2001","key":"ref2"},{"journal-title":"Virtex-E 1 8V Extended Memory Field-Programmable Gate Arrays Datasheet","year":"2001","key":"ref1"},{"article-title":"Architectures and Algorithms for Laser-Programmed Gate Arrays with Foldable Logic Blocks","year":"1997","author":"anderson","key":"ref9"}],"event":{"name":"IEEE 2002 Custom Integrated Circuits Conference","acronym":"CICC-02","location":"Orlando, FL, USA"},"container-title":["Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7911\/21814\/01012768.pdf?arnumber=1012768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:40:59Z","timestamp":1497566459000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1012768\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/cicc.2002.1012768","relation":{},"subject":[]}}