{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T00:38:29Z","timestamp":1725496709641},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2003.1249356","type":"proceedings-article","created":{"date-parts":[[2004,1,23]],"date-time":"2004-01-23T23:33:03Z","timestamp":1074900783000},"page":"45-48","source":"Crossref","is-referenced-by-count":8,"title":["SoC implementation issues for synthesizable embedded programmable logic cores"],"prefix":"10.1109","author":[{"given":"J.C.H.","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"Aken'Ova","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.J.E.","family":"Wilton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Saleh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Leopard Logic Inc","article-title":"HyperBlox FP Embedded FPGA Cores","year":"2002","key":"ref4"},{"journal-title":"Actel Corp","article-title":"VariCore Embedded Programmable Gate Array Core (EPGA) 0.18&#x00B5;m Family","year":"2001","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.2001.946668"},{"journal-title":"eASIC","article-title":"eASIC 0.13&#x00B5;m Core","year":"0","key":"ref6"},{"journal-title":"M2000 Inc","article-title":"M2000 FLEXEOStm Configurable IP Core","year":"0","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929725"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.808288"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929724"},{"key":"ref9","first-page":"1","article-title":"Architectures and Algorithms for Syntbesizable Embedded Programmable Logic Cores","author":"kafafl","year":"2003","journal-title":"Proceedings of the ACM International Symposium on Field-programmable Gate Arrays"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2002.1012755"}],"event":{"name":"CICC Custom Integrated Circuits Conference","acronym":"CICC-03","location":"San Jose, CA, USA"},"container-title":["Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8830\/27953\/01249356.pdf?arnumber=1249356","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T14:52:47Z","timestamp":1489416767000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1249356\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/cicc.2003.1249356","relation":{},"subject":[]}}