{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T15:29:13Z","timestamp":1742398153035,"version":"3.28.0"},"reference-count":41,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2003.1249391","type":"proceedings-article","created":{"date-parts":[[2004,2,3]],"date-time":"2004-02-03T14:24:01Z","timestamp":1075818241000},"page":"207-213","source":"Crossref","is-referenced-by-count":5,"title":["Three dimensional CMOS devices and integrated circuits"],"prefix":"10.1109","author":[{"family":"Meikei Ieong","sequence":"first","affiliation":[]},{"given":"K.W.","family":"Guarini","sequence":"additional","affiliation":[]},{"given":"V.","family":"Chan","sequence":"additional","affiliation":[]},{"given":"K.","family":"Bernstein","sequence":"additional","affiliation":[]},{"given":"R.","family":"Joshi","sequence":"additional","affiliation":[]},{"given":"J.","family":"Kedzierski","sequence":"additional","affiliation":[]},{"given":"W.","family":"Haensch","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996742"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2003.1194993"},{"key":"ref33","first-page":"33","article-title":"Fabrication technologies for three-dimensional integrated circuits","author":"rcif","year":"2002","journal-title":"Proc IEEE International Symposium on Quality Electronic Design"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2002.1175992"},{"key":"ref31","first-page":"161","article-title":"Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films","author":"chan","year":"2000","journal-title":"IEDM Tech Dig"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/16.711358"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/MCMC.1994.292526"},{"key":"ref36","first-page":"667","article-title":"3-D memory for improved system performance","volume":"1","author":"forthun","year":"1992","journal-title":"Proc Int Electronic Packaging Conf"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/96.659500"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.1990.110988"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2001.930045"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979532"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979527"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1998.746531"},{"key":"ref14","first-page":"60","article-title":"Sub 50-nm FinFET: PMOS","author":"huang","year":"1999","journal-title":"IEDM Tech Dig"},{"key":"ref15","first-page":"437","article-title":"High-Performance Symmetric-Gate and CMOS-Compatible Vt Asymmetric-Gate FinFET Devices","author":"kedzierski","year":"2001","journal-title":"IEDM Tech Dig"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2002.1029499"},{"key":"ref17","first-page":"411","article-title":"A Functional FinFET -DGCMOS SRAM Cell","author":"nowak","year":"2002","journal-title":"IEDM Tech Dig"},{"key":"ref18","first-page":"42","article-title":"Transistor Elements for 30nm Physical Gate Lengths and Beyond","author":"doyle","year":"2002","journal-title":"Intel Tech Jour"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/55.936358"},{"key":"ref28","first-page":"117","article-title":"Multi-layers with buried structures (MLBS): An approach to three dimensional integration","author":"xue","year":"2001","journal-title":"Proc IEEE Int'l SOI Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0121"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2000.854268"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"ref6","first-page":"267","article-title":"Extreme Scaling with Ultra-Thin Si Channel MOSFETs","author":"doris","year":"2002","journal-title":"IEDM Tech Dig"},{"key":"ref29","first-page":"638","article-title":"Application of E-Beam Recrystallization to Three Layer Image Processor Fabrication","volume":"48","author":"haxama","year":"2001","journal-title":"IEEE Trans Electron Devices"},{"key":"ref5","first-page":"136","article-title":"Ultra-thin Silicon Channel Single- and Double-gate MOSFETs","author":"ieong","year":"2002","journal-title":"Ext Abst of SSDM"},{"key":"ref8","article-title":"Challenges and Opportunities of Ultrathin Channel Single- and Multiple-gate MOSFET's","author":"leong","year":"2003","journal-title":"Proc Ultimate Integration Silicon (ULIS)"},{"key":"ref7","first-page":"51","article-title":"Examination of Hole Mobility in Ultra-thin Body SOI MOSFETs","author":"ren","year":"2002","journal-title":"IEDM Tech Dig"},{"journal-title":"Semiconductor Industry Association International Technology Roadrnap for Semiconductors","year":"0","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2001.934946"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1996.554044"},{"key":"ref20","first-page":"255","article-title":"25 nm Omega FET","author":"yang","year":"2002","journal-title":"IEDM Tech Dig"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1999.823850"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1990.237128"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/342001.339691"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-7091-6244-6_53"},{"key":"ref23","first-page":"52","article-title":"A highly manufacturable 110 nm DRAM technology with 8F**2 vertical transistor cell for 1 Gb and beyond","author":"akatsu","year":"2002","journal-title":"Symp on VLSI Tech Dig"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2001.979560"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/5.915376"}],"event":{"name":"CICC Custom Integrated Circuits Conference","acronym":"CICC-03","location":"San Jose, CA, USA"},"container-title":["Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8830\/27953\/01249391.pdf?arnumber=1249391","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T14:57:43Z","timestamp":1489417063000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1249391\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":41,"URL":"https:\/\/doi.org\/10.1109\/cicc.2003.1249391","relation":{},"subject":[]}}