{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:47:00Z","timestamp":1759146420119},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2003.1249472","type":"proceedings-article","created":{"date-parts":[[2004,3,1]],"date-time":"2004-03-01T21:26:50Z","timestamp":1078176410000},"page":"617-620","source":"Crossref","is-referenced-by-count":38,"title":["Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process"],"prefix":"10.1109","author":[{"given":"P.","family":"Hazucha","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Karnik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Walstra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.","family":"Bloechel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Tschanz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Maiz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Soumyanath","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Dermer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Narendra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.","family":"De","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Borkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015084"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2001.934195"},{"key":"ref6","first-page":"61","article-title":"A 90nm logic technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low kILD and 1um2SRAM cell","author":"thompson","year":"2002","journal-title":"IEDM 2002"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/23.903813"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/16.701475"}],"event":{"name":"CICC Custom Integrated Circuits Conference","acronym":"CICC-03","location":"San Jose, CA, USA"},"container-title":["Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8830\/27953\/01249472.pdf?arnumber=1249472","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T15:24:33Z","timestamp":1489418673000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1249472\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/cicc.2003.1249472","relation":{},"subject":[]}}