{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T16:29:00Z","timestamp":1771518540470,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2004.1358788","type":"proceedings-article","created":{"date-parts":[[2004,11,30]],"date-time":"2004-11-30T19:56:05Z","timestamp":1101844565000},"page":"243-246","source":"Crossref","is-referenced-by-count":11,"title":["A 3D mixed-mode ESD protection circuit simulation-design methodology"],"prefix":"10.1109","author":[{"given":"H.","family":"Xie","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Zhan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.","family":"Feng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Gafiteanu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.811978"},{"key":"ref3","first-page":"7","article-title":"A review of EOS\/ESD field failures in military equipment","author":"green","year":"1998","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref6","article-title":"Taurus-Device User Guide","year":"2003"},{"key":"ref5","article-title":"Taurus-Process User Guide","year":"2003"},{"key":"ref8","first-page":"745","article-title":"Simulation of Si-Ge BiCMOS ESD Structures Operations Including Spatial Current Instability Mode","author":"vashchenko","year":"2003","journal-title":"Proc MIEL"},{"key":"ref7","article-title":"Modeling of Electrical Overstress in Integrated Circuits","author":"diaz","year":"1994"},{"key":"ref2","first-page":"233","article-title":"ESD design methodology","author":"merri","year":"1993","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref9","first-page":"85","article-title":"TLP Calibration, Correlation, Standards, and New Techniques","author":"barth","year":"2000","journal-title":"Proc EOS\/ESD Symp"},{"key":"ref1","author":"wang","year":"2002","journal-title":"On-Chip ESD Protection for Integrated Circuits"}],"event":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference","location":"Orlando, FL, USA","acronym":"CICC-04"},"container-title":["Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9389\/29800\/01358788.pdf?arnumber=1358788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T16:59:12Z","timestamp":1489510752000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1358788\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/cicc.2004.1358788","relation":{},"subject":[]}}