{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:21:37Z","timestamp":1729628497208,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2004.1358891","type":"proceedings-article","created":{"date-parts":[[2004,11,30]],"date-time":"2004-11-30T14:56:05Z","timestamp":1101826565000},"page":"583-586","source":"Crossref","is-referenced-by-count":0,"title":["A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors"],"prefix":"10.1109","author":[{"family":"Young-Don Bae","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"In-Cheol Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.2004.1260972"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.881217"},{"year":"2003","key":"ref10","article-title":"A Next-Generation Packet Processor for Wireless Networking"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269203"},{"year":"0","key":"ref11","article-title":"APEX 20K Devices: System-on-a-Programmable-Chip Solutions"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196113"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2002.800865"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/30.713217"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.808288"},{"key":"ref9","article-title":"A Multithreading Extension for Low-Power, Low-Cost Applications","author":"norden","year":"2003","journal-title":"Proc Embedded Processor Forum"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"1703","DOI":"10.1109\/JSSC.2003.817259","article-title":"A Single-Chip Programmable Platform Based on a Multithreaded Processor and Configurable Logic Clusters","volume":"38","author":"young-don","year":"0","journal-title":"IEEE Journal of Solid-State Circuits"}],"event":{"name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference","acronym":"CICC-04","location":"Orlando, FL, USA"},"container-title":["Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9389\/29800\/01358891.pdf?arnumber=1358891","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T08:33:34Z","timestamp":1497602014000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1358891\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/cicc.2004.1358891","relation":{},"subject":[]}}