{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:22:44Z","timestamp":1729653764815,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/cicc.2005.1568725","type":"proceedings-article","created":{"date-parts":[[2006,1,18]],"date-time":"2006-01-18T18:42:54Z","timestamp":1137609774000},"page":"532-539","source":"Crossref","is-referenced-by-count":12,"title":["A digital clock and data recovery architecture for multi-gigabit\/s binary links"],"prefix":"10.1109","author":[{"given":"J.","family":"Sonntag","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Stonick","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/4.641688"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/SSMSD.2003.1190436"},{"key":"11","first-page":"65","article-title":"A 0.6 to 9.6Gb\/s Binary Backplane Transceiver Core in 0.13 ? CMOS","author":"krishna","year":"2005","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494044"},{"key":"3","doi-asserted-by":"crossref","first-page":"735","DOI":"10.1109\/JSSC.2005.843624","article-title":"A 10-Gb\/s CMOS clock and data recovery circuit with an analog phase interpolator","volume":"40","author":"kreienkamp","year":"2005","journal-title":"IEEE J Solid-State Circuits"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1205927"},{"key":"1","first-page":"34","article-title":"Designing bang-bang PLL's for clock and data recovery in serial data transmission systems","author":"walker","year":"2003","journal-title":"Phase-Locking in High-Performance Systems"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810045"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818577"},{"journal-title":"Nonlinear Control Engineering","year":"1975","author":"atherton","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2002.1187056"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831600"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831457"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2001.912547"}],"event":{"name":"IEEE 2005 Custom Integrated Circuits Conference, 2005.","location":"San Jose, CA, USA"},"container-title":["Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10489\/33245\/01568725.pdf?arnumber=1568725","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T22:30:11Z","timestamp":1497652211000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1568725\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/cicc.2005.1568725","relation":{},"subject":[]}}