{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:53:37Z","timestamp":1725785617269},"reference-count":21,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1109\/cicc.2007.4405808","type":"proceedings-article","created":{"date-parts":[[2008,7,18]],"date-time":"2008-07-18T17:19:35Z","timestamp":1216401575000},"page":"619-622","source":"Crossref","is-referenced-by-count":4,"title":["Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization"],"prefix":"10.1109","author":[{"given":"Rasit Onur","family":"Topaloglu","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1557\/PROC-0913-D05-05"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249396"},{"key":"18","doi-asserted-by":"crossref","first-page":"143","DOI":"10.1109\/SISPAD.2005.201493","article-title":"the impact of layout on stress-enhanced transistor performance","author":"moroz","year":"2005","journal-title":"2005 International Conference On Simulation of Semiconductor Processes and Devices"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.831358"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/16.944190"},{"key":"13","first-page":"158","article-title":"an optimized densification of the filled oxide for quarter micron shallow trench isolation (sti), symp. on vlsi technology","author":"lee","year":"1996","journal-title":"Digest of technical papers"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.841286(410) 52"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRev.94.42"},{"year":"0","key":"12"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884070"},{"key":"3","article-title":"characteristics of high performance pfets with embedded sige source\/drain and 100 channels on 45 rotated wafers","author":"ouyang","year":"2005","journal-title":"Int Symp"},{"key":"20","doi-asserted-by":"crossref","DOI":"10.1109\/ISQED.2006.124","article-title":"stressaware design methodology","author":"moroz","year":"2006","journal-title":"IEEE Int Symp Quality Electronic Design"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346958"},{"article-title":"modeling of mechanical stress in silicon isolation technology and its influence on device characteristics","year":"1999","author":"rueda","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2004.1345390"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609265"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.872693"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469199"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346959"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2006.1705225"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419385"}],"event":{"name":"2007 IEEE Custom Integrated Circuits Conference","start":{"date-parts":[[2007,9,16]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,9,19]]}},"container-title":["2007 IEEE Custom Integrated Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4405666\/4405667\/04405808.pdf?arnumber=4405808","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,12]],"date-time":"2019-05-12T19:33:47Z","timestamp":1557689627000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4405808\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/cicc.2007.4405808","relation":{},"subject":[],"published":{"date-parts":[[2007]]}}}