{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T22:11:55Z","timestamp":1725660715323},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,9]]},"DOI":"10.1109\/cicc.2007.4405849","type":"proceedings-article","created":{"date-parts":[[2008,7,21]],"date-time":"2008-07-21T17:16:34Z","timestamp":1216660594000},"page":"795-798","source":"Crossref","is-referenced-by-count":4,"title":["A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST"],"prefix":"10.1109","author":[{"given":"Darren","family":"Anand","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jim","family":"Covino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeffrey","family":"Dreibelbis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Fifield","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kevin","family":"Gorman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Jacunski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jake","family":"Paparelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gary","family":"Pomichter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dale","family":"Pontius","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Roberge","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephen","family":"Sliva","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332665"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883344"},{"key":"1","first-page":"7","article-title":"deep sub-100nm design challenges","author":"furuyama","year":"2006","journal-title":"IEEE ASSCC"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1147\/rd.466.0675"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/4.726568"}],"event":{"name":"2007 IEEE 29th Custom Integrated Circuits Conference","start":{"date-parts":[[2007,9,16]]},"location":"San Jose, CA","end":{"date-parts":[[2007,9,19]]}},"container-title":["2007 IEEE Custom Integrated Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4405666\/4405667\/04405849.pdf?arnumber=4405849","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,12,10]],"date-time":"2018-12-10T20:47:18Z","timestamp":1544474838000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4405849\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,9]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/cicc.2007.4405849","relation":{},"subject":[],"published":{"date-parts":[[2007,9]]}}}