{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,30]],"date-time":"2025-04-30T22:40:05Z","timestamp":1746052805483,"version":"3.28.0"},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/cicc.2011.6055361","type":"proceedings-article","created":{"date-parts":[[2011,10,21]],"date-time":"2011-10-21T11:03:36Z","timestamp":1319195016000},"page":"1-4","source":"Crossref","is-referenced-by-count":5,"title":["A 19 mW\/lane Serdes transceiver for SFI-5.1 application"],"prefix":"10.1109","author":[{"given":"Siavash","family":"Fallahi","sequence":"first","affiliation":[]},{"given":"Delong","family":"Cui","sequence":"additional","affiliation":[]},{"given":"Deyi","family":"Pi","sequence":"additional","affiliation":[]},{"given":"Rose","family":"Zhu","sequence":"additional","affiliation":[]},{"given":"Greg","family":"Unruh","sequence":"additional","affiliation":[]},{"given":"Marcel","family":"Lugthart","sequence":"additional","affiliation":[]},{"given":"Afshin","family":"Momtaz","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"37","article-title":"An ASIC-ready 1.25–6.25Gb\/s serdes in 90nm CMOS with multi-standard compatibility","author":"nishi","year":"2008","journal-title":"IEEE Asian Solid-State Circuits Conf"},{"key":"ref3","first-page":"384","article-title":"A quad 3.125Gbps transceiver cell with all-digital data recovery circuits","author":"lee","year":"0","journal-title":"Symposium on VLSI Circuits Digest of Technical Papers"},{"key":"ref6","first-page":"177","article-title":"A 5Gb\/s low-power PCI Express\/USB 3. 0 ready PHY in 40nm CMOS technology with high-jitter immunity","author":"lin","year":"2009","journal-title":"IEEE Asian Solid-State Circuits Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320970"},{"key":"ref2","first-page":"487","article-title":"A 2.5Gbps - 3.125Gps multi-core serial-link transceiver in 0.13 µm CMOS","author":"geurts","year":"2004","journal-title":"IEEE Solid-State Circuit Conference 2004 ESSCIRC 2004"},{"key":"ref1","article-title":"Serdes framer interface level 5 (SFI-5)","volume":"29","year":"2002","journal-title":"Optical Internetworking Forum"}],"event":{"name":"2011 IEEE Custom Integrated Circuits Conference - CICC 2011","start":{"date-parts":[[2011,9,19]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2011,9,21]]}},"container-title":["2011 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6045019\/6055276\/06055361.pdf?arnumber=6055361","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T11:13:17Z","timestamp":1490094797000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6055361\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/cicc.2011.6055361","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}