{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:56:29Z","timestamp":1725785789182},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/cicc.2011.6055367","type":"proceedings-article","created":{"date-parts":[[2011,10,21]],"date-time":"2011-10-21T15:03:36Z","timestamp":1319209416000},"page":"1-8","source":"Crossref","is-referenced-by-count":4,"title":["Power-efficient I\/O design considerations for high-bandwidth applications"],"prefix":"10.1109","author":[{"given":"John C.","family":"Eble","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Scott","family":"Best","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brian","family":"Leibowitz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Luo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Robert","family":"Palmer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Wilson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jared","family":"Zerbe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amir","family":"Amirkhany","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nhat","family":"Nguyen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"270","article-title":"A scalable 5–15Gbps, 14–75mW low power I\/O transceiver in 65nm CMOS","author":"balamurugan","year":"2007","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref11","first-page":"156","article-title":"A 47×10Gb\/s l.4mW\/(Gb\/s) parallel interface in 45nm CMOS","author":"o'mahoney","year":"2010","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.443"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040230"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818300"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085991"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108120"},{"key":"ref17","article-title":"A 5.6Gb\/s 2.4mW\/Gb\/s bidirectional link with 8ns power-on","author":"zerbe","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2079450"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.881205"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433825"},{"key":"ref3","first-page":"97","article-title":"A 10mW 3.6Gbps I\/O Transmitter","author":"hatamkhani","year":"2003","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.881204"},{"key":"ref5","article-title":"A 12.8-Gb\/s\/link tri-modal single-ended memory interface for graphics applications","author":"amirkhany","year":"2011","journal-title":"Symp VLSI Circuits Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705296"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.825259"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672180"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908692"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696055"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2076550"},{"journal-title":"MCL SiP technology that achieves both wide bandwidth and low power","year":"2007","key":"ref22"},{"journal-title":"Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency","year":"2010","author":"dorsey","key":"ref21"}],"event":{"name":"2011 IEEE Custom Integrated Circuits Conference - CICC 2011","start":{"date-parts":[[2011,9,19]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2011,9,21]]}},"container-title":["2011 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6045019\/6055276\/06055367.pdf?arnumber=6055367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T15:16:31Z","timestamp":1490109391000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6055367\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/cicc.2011.6055367","relation":{},"subject":[],"published":{"date-parts":[[2011,9]]}}}