{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T10:24:45Z","timestamp":1725618285605},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/cicc.2014.6946033","type":"proceedings-article","created":{"date-parts":[[2014,11,12]],"date-time":"2014-11-12T22:50:10Z","timestamp":1415832610000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors"],"prefix":"10.1109","author":[{"given":"Alex","family":"Park","sequence":"first","affiliation":[]},{"given":"Venkat","family":"Narayanan","sequence":"additional","affiliation":[]},{"given":"Keith","family":"Bowman","sequence":"additional","affiliation":[]},{"given":"Francois","family":"Atallah","sequence":"additional","affiliation":[]},{"given":"Alain","family":"Artieri","sequence":"additional","affiliation":[]},{"given":"Sei Seung","family":"Yoon","sequence":"additional","affiliation":[]},{"given":"Kendrick","family":"Yuen","sequence":"additional","affiliation":[]},{"given":"David","family":"Hansquine","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"238","article-title":"A 16nm 128Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-VMinApplications","author":"chen","year":"2014","journal-title":"IEEE ISSCC"},{"key":"ref3","first-page":"232","article-title":"A 14nm FinFET 128Mb 6T SRAM with VMIN-Enhancement Technique for Low-Power Applications","author":"song","year":"2014","journal-title":"IEEE ISSCC"},{"key":"ref6","first-page":"132c","article-title":"A 22nm 2.5MB Slice On-Die L3 Cache for the Next Generation Xeon&#x00AE; Processor","author":"chen","year":"2013","journal-title":"IEEE Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2004.14"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000118"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2012.6232861"},{"key":"ref2","first-page":"316","article-title":"A 20nm 112Mb SRAM in High-k Metal-gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications","author":"chang","year":"2013","journal-title":"IEEE ISSCC"},{"key":"ref1","first-page":"230","article-title":"A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active VMIN-Enhancing Assist Circuitry","author":"karl","year":"2012","journal-title":"IEEE ISSCC"}],"event":{"name":"2014 IEEE Custom Integrated Circuits Conference - CICC 2014","start":{"date-parts":[[2014,9,15]]},"location":"San Jose, CA","end":{"date-parts":[[2014,9,17]]}},"container-title":["Proceedings of the IEEE 2014 Custom Integrated Circuits Conference"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6924030\/6945974\/06946033.pdf?arnumber=6946033","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,11]],"date-time":"2020-11-11T22:10:47Z","timestamp":1605132647000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6946033\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/cicc.2014.6946033","relation":{},"subject":[],"published":{"date-parts":[[2014,9]]}}}