{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,27]],"date-time":"2025-07-27T07:18:16Z","timestamp":1753600696141},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1109\/cicc.2015.7338357","type":"proceedings-article","created":{"date-parts":[[2015,11,30]],"date-time":"2015-11-30T16:52:45Z","timestamp":1448902365000},"source":"Crossref","is-referenced-by-count":15,"title":["Design considerations of HBM stacked DRAM and the memory architecture extension"],"prefix":"10.1109","author":[{"given":"Dong Uk","family":"Lee","sequence":"first","affiliation":[]},{"given":"Kang Seol","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Yongwoo","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Kyung Whan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jong Ho","family":"Kang","sequence":"additional","affiliation":[]},{"given":"Jaejin","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jun Hyun","family":"Chun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2085991"},{"key":"ref11","year":"2012"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015395"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011042"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908004"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487803"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6176900"},{"key":"ref17","first-page":"735","article-title":"Use of MISRs for Compression and Diagnostics","author":"keller","year":"2005","journal-title":"Proc International Test Conference (ITC)"},{"key":"ref18","first-page":"605","article-title":"Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links","author":"loke","year":"2009","journal-title":"the IEEE Custom Integrated Circuits Conference"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2010.2101771"},{"key":"ref28","article-title":"Design Technologies for a 1.2V 2.4Gb\/s\/pin High Capacity DDR4 SDRAM with TSVs","author":"oh","year":"2014","journal-title":"Symposium on VLSI Technology Digest of Technical Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164731"},{"key":"ref27","first-page":"615","article-title":"Tiered-latency DRAM: A low latency and low cost DRAM architecture","author":"lee","year":"2013","journal-title":"International Symposium on High Performance Computer Architecture"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237004"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757362"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2242251"},{"key":"ref5","first-page":"18","article-title":"Advancing High Performance Heterogeneous Integration Through Die Stacking","author":"madden","year":"2012","journal-title":"European Solid-State Device Research Conference (ESSDERC)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2360379"},{"key":"ref7","first-page":"16c","article-title":"An extra low-power 1Tbit\/s bandwidth PLL\/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application","author":"lin","year":"2013","journal-title":"Symposium on VLSI Circuits Digest of Technical Papers"},{"key":"ref2","first-page":"2","article-title":"System Scaling and Collaborative Open Innovation","author":"sun","year":"2013","journal-title":"Symposium on VLSI Technology Digest of Technical Papers"},{"key":"ref9","year":"2013"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858357"},{"key":"ref20","article-title":"TSV Technology and Challenges for 3D Stacked DRAM","author":"lee","year":"2014","journal-title":"Symposium on VLSI Technology Digest of Technical Papers"},{"key":"ref22","first-page":"278","article-title":"A 60nm 6Gb\/s\/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI\/SSN-Reduction Techniques","author":"bae","year":"2008","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref21","article-title":"An exact measurement and repair circuit of TSV connections for 128GB\/s high-bandwidth memory(HBM) stacked DRAM","author":"lee","year":"2014","journal-title":"Symposium on VLSI Circuits Digest of Technical Papers"},{"key":"ref24","article-title":"A semiconductor memory development and manufacturing perspective","author":"atwood","year":"2014","journal-title":"European Solid-State Device Research Conference (ESSDERC)"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1999.797260"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"368","DOI":"10.1145\/2366231.2337202","article-title":"A case for exploiting subarray-Ievel parallelism (SALP) in DRAM","author":"kim","year":"2012","journal-title":"International Symposium on Computer Architecture (ISCA)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034417"}],"event":{"name":"2015 IEEE Custom Integrated Circuits Conference - CICC 2015","location":"San Jose, CA, USA","start":{"date-parts":[[2015,9,28]]},"end":{"date-parts":[[2015,9,30]]}},"container-title":["2015 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7321938\/7338356\/07338357.pdf?arnumber=7338357","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T20:43:43Z","timestamp":1498250623000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7338357\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,9]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/cicc.2015.7338357","relation":{},"subject":[],"published":{"date-parts":[[2015,9]]}}}