{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,12]],"date-time":"2025-12-12T13:30:58Z","timestamp":1765546258622},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/cicc.2017.7993609","type":"proceedings-article","created":{"date-parts":[[2017,8,9]],"date-time":"2017-08-09T20:07:33Z","timestamp":1502309253000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies"],"prefix":"10.1109","author":[{"given":"Sanu","family":"Mathew","sequence":"first","affiliation":[]},{"given":"Sudhir","family":"Satpathy","sequence":"additional","affiliation":[]},{"given":"Vikram","family":"Suresh","sequence":"additional","affiliation":[]},{"given":"Ram K.","family":"Krishnamurthy","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"250","article-title":"A 3.07?m2\/bitcell Physically Unclonable Function with 3.5% and 1% Bit-Instability across 0 to 80°C and 0.6 to 1.2V in a 65nm CMOS","author":"li","year":"2015","journal-title":"Symposium on VLSI Circuits Digest of Technical Papers"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/JSSC.2014.2384039"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ICCD.2016.7753358"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/ESSCIRC.2014.6942066"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ISSCC.2014.6757433"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/JSSC.2012.2217631"},{"key":"ref7","first-page":"116","article-title":"?RNG: A 300-950mV 323Gbps\/W all-digital full-entropy TRNG in 14nm FinFET CMOS","author":"mathew","year":"2015","journal-title":"Proc of IEEE ESSCIRC"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/ISSCC.2009.4977309"},{"key":"ref9","article-title":"A Robust ?40 to 120°C All-Digital True Random Number Generator in 40nm CMOS","author":"yang","year":"2015","journal-title":"Symposium on VLSI Circuits Dig Tech Papers"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/JSSC.2011.2108131"}],"event":{"name":"2017 IEEE Custom Integrated Circuits Conference (CICC)","start":{"date-parts":[[2017,4,30]]},"location":"Austin, TX","end":{"date-parts":[[2017,5,3]]}},"container-title":["2017 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7986634\/7993450\/07993609.pdf?arnumber=7993609","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,8,29]],"date-time":"2017-08-29T19:38:38Z","timestamp":1504035518000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7993609\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/cicc.2017.7993609","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}