{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T12:58:00Z","timestamp":1730206680684,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/cicc.2018.8357073","type":"proceedings-article","created":{"date-parts":[[2018,5,18]],"date-time":"2018-05-18T21:27:22Z","timestamp":1526678842000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["A 3.125-to-28.125 Gb\/s multi-standard transceiver with a fully channel-independent operation in 40nm CMOS"],"prefix":"10.1109","author":[{"given":"Jong-Hyeok","family":"Yoon","sequence":"first","affiliation":[]},{"given":"Kyeongha","family":"Kwon","sequence":"additional","affiliation":[]},{"given":"Hyeon-Min","family":"Bae","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"428","DOI":"10.1109\/JSSC.2015.2497963","article-title":"A 4-to-10.5 Gb\/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition","volume":"51","author":"shu","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2646803"},{"key":"ref6","first-page":"194","article-title":"A 185fsrms-integrated-jitter and ?245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector","author":"choi","year":"2016","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870476"},{"key":"ref8","first-page":"1","article-title":"A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS","author":"elkholy","year":"2015","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref7","first-page":"1","article-title":"A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ\/b optical receiver in 28nm FDSOI CMOS","author":"raj","year":"2015","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2014.6946023"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2369494"},{"key":"ref1","first-page":"184","article-title":"A 650Mb\/s-to-8Gb\/s referenceless CDR circuit with automatic acquisition of data rate","author":"lee","year":"2009","journal-title":"ISSCC Dig Tech Papers"}],"event":{"name":"2018 IEEE Custom Integrated Circuits Conference (CICC)","start":{"date-parts":[[2018,4,8]]},"location":"San Diego, CA","end":{"date-parts":[[2018,4,11]]}},"container-title":["2018 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8355238\/8357004\/08357073.pdf?arnumber=8357073","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,26]],"date-time":"2022-01-26T03:26:58Z","timestamp":1643167618000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8357073\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/cicc.2018.8357073","relation":{},"subject":[],"published":{"date-parts":[[2018,4]]}}}