{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T14:31:38Z","timestamp":1784212298167,"version":"3.55.0"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/cicc.2019.8780235","type":"proceedings-article","created":{"date-parts":[[2019,8,2]],"date-time":"2019-08-02T00:03:04Z","timestamp":1564704184000},"page":"1-4","source":"Crossref","is-referenced-by-count":9,"title":["A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power"],"prefix":"10.1109","author":[{"given":"Alessio","family":"Santiccioli","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mario","family":"Mercandelli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrea L.","family":"Lacaita","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Carlo","family":"Samori","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Salvatore","family":"Levantino","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177036"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598277"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.925948"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2688384"},{"key":"ref5","first-page":"252","article-title":"A 0.048mm 2,3 mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique","author":"deng","year":"2015","journal-title":"ISSCC Dig of Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357041"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2018.8429041"},{"key":"ref2","first-page":"326","article-title":"A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection","author":"kundu","year":"2016","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.4577"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757469"}],"event":{"name":"2019 IEEE Custom Integrated Circuits Conference (CICC)","location":"Austin, TX, USA","start":{"date-parts":[[2019,4,14]]},"end":{"date-parts":[[2019,4,17]]}},"container-title":["2019 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8767369\/8780115\/08780235.pdf?arnumber=8780235","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:51:45Z","timestamp":1658155905000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8780235\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/cicc.2019.8780235","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}