{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T16:51:41Z","timestamp":1781715101537,"version":"3.54.5"},"reference-count":33,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/cicc.2019.8780346","type":"proceedings-article","created":{"date-parts":[[2019,8,2]],"date-time":"2019-08-02T00:03:04Z","timestamp":1564704184000},"page":"1-8","source":"Crossref","is-referenced-by-count":6,"title":["Analog\/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond"],"prefix":"10.1109","author":[{"given":"Alvin L. S.","family":"Loke","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Da","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tin Tin","family":"Wee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jonathan L.","family":"Holland","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Patrick","family":"Isakanian","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kern","family":"Rim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sam","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jacob S.","family":"Schneider","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giri","family":"Nallapati","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sreeker","family":"Dundigal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hasnain","family":"Lakdawala","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Behnam","family":"Amelifard","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chulkyu","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Betty","family":"McGovern","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paul S.","family":"Holdaway","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiaohua","family":"Kong","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Burton M.","family":"Leary","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131614"},{"key":"ref32","author":"xi","year":"2003","journal-title":"BSIM4 3 0 MOSFET Model User Manual"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2002.1175792"},{"key":"ref30","article-title":"Layout-induced stress effects in 14nm & 10nm finFETs and their impact on performance","author":"garcia bardon","year":"2013","journal-title":"IEEE Symp VLSI Technology"},{"key":"ref10","article-title":"SoC scaling challenges in the era of the single digit technology nodes","author":"yang","year":"2017","journal-title":"Int Workshop Advanced Patterning Solutions"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSM.2006.4493084"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588589"},{"key":"ref13","article-title":"A spacer patterning technology for nanoscale CMOS","volume":"49","author":"choi","year":"2002","journal-title":"IEEE Trans Electron Devices"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268472"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409674"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2009.5090400"},{"key":"ref17","article-title":"28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications","author":"h","year":"2011","journal-title":"IEEE CICC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796628"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2000.904419"},{"key":"ref28","article-title":"Design and technology co-optimization for mobile SoCs","author":"terzioglu","year":"2015","journal-title":"IEEE ICICDT"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573359"},{"key":"ref27","article-title":"ADT7461 ±1°C temperature monitor with series resistance cancellation","year":"2014","journal-title":"Semiconductors"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724591"},{"key":"ref6","article-title":"High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors","author":"packan","year":"2009","journal-title":"IEEE IEDM"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2010.5617407"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838333"},{"key":"ref8","article-title":"Analog\/RF wonderland: circuit and technology co-optimization in advanced finFET technology","author":"hsueh","year":"2016","journal-title":"IEEE Symp VLSI Technology"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.7567\/SSDM.2009.E-3-2L"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2012.6242496"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870240"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2007.4405845"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568758"},{"key":"ref22","article-title":"10 nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling","author":"yang","year":"2017","journal-title":"IEEE Symp VLSI Technology"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2013.6724597"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2014.6894381"},{"key":"ref23","article-title":"Device challenges for scaled analog-RF","author":"hsueh","year":"2017","journal-title":"IEEE Symp VLSI Technology Short Course"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.760378"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047076"}],"event":{"name":"2019 IEEE Custom Integrated Circuits Conference (CICC)","location":"Austin, TX, USA","start":{"date-parts":[[2019,4,14]]},"end":{"date-parts":[[2019,4,17]]}},"container-title":["2019 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8767369\/8780115\/08780346.pdf?arnumber=8780346","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:51:20Z","timestamp":1658155880000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8780346\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/cicc.2019.8780346","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}