{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T13:46:26Z","timestamp":1770039986614,"version":"3.49.0"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/cicc48029.2020.9075947","type":"proceedings-article","created":{"date-parts":[[2020,4,24]],"date-time":"2020-04-24T00:53:24Z","timestamp":1587689604000},"page":"1-4","source":"Crossref","is-referenced-by-count":13,"title":["A 32Gb\/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol"],"prefix":"10.1109","author":[{"given":"Mike","family":"Bichan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Clifford","family":"Ting","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bahram","family":"Zand","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ruslana","family":"Shulyzki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Guthrie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Katya","family":"Tyshchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junhong","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alireza","family":"Parsafar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eric","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aynaz","family":"Vatankhahghadim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaham","family":"Sharifian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aleksey","family":"Tyshchenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"De Vita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Syed","family":"Rubab","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sitaraman","family":"Iyer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fulvio","family":"Spagna","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Noam","family":"Dolev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357111"},{"key":"ref3","first-page":"314","article-title":"A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup-Hold Time","author":"schinkel","year":"2007","journal-title":"ISSCC Dig of Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417906"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417908"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310206"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573471"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268472"},{"key":"ref9","first-page":"114","article-title":"A 60Gb\/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ\/b at 32dB Loss","author":"lacroix","year":"2019","journal-title":"ISSCC Dig of Tech Papers"},{"key":"ref1","year":"0","journal-title":"PCI Express Base Specification"}],"event":{"name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","location":"Boston, MA, USA","start":{"date-parts":[[2020,3,22]]},"end":{"date-parts":[[2020,3,25]]}},"container-title":["2020 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9060424\/9075871\/09075947.pdf?arnumber=9075947","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T15:45:36Z","timestamp":1656344736000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9075947\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/cicc48029.2020.9075947","relation":{},"subject":[],"published":{"date-parts":[[2020,3]]}}}