{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:18:38Z","timestamp":1766067518060},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,4]]},"DOI":"10.1109\/cicc53496.2022.9772831","type":"proceedings-article","created":{"date-parts":[[2022,5,18]],"date-time":"2022-05-18T19:37:56Z","timestamp":1652902676000},"source":"Crossref","is-referenced-by-count":10,"title":["System technology co-optimization and design challenges for 3D IC"],"prefix":"10.1109","author":[{"given":"Supreet","family":"Jeloka","sequence":"first","affiliation":[{"name":"Arm Inc.,USA"}]},{"given":"Brian","family":"Cline","sequence":"additional","affiliation":[{"name":"Arm Inc.,USA"}]},{"given":"Shidhartha","family":"Das","sequence":"additional","affiliation":[{"name":"Arm Ltd.,UK"}]},{"given":"Benoit","family":"Labbe","sequence":"additional","affiliation":[{"name":"Arm Ltd.,UK"}]},{"given":"Alejandro","family":"Rico","sequence":"additional","affiliation":[{"name":"Arm Inc.,USA"}]},{"given":"Rainer","family":"Herberholz","sequence":"additional","affiliation":[{"name":"Arm Ltd.,UK"}]},{"given":"Javier","family":"DeLaCruz","sequence":"additional","affiliation":[{"name":"Arm Inc.,USA"}]},{"given":"Rahul","family":"Mathur","sequence":"additional","affiliation":[{"name":"Arm Inc.,USA"}]},{"given":"Shawn","family":"Hung","sequence":"additional","affiliation":[{"name":"Arm Inc.,USA"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM13553.2020.9372120"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1038\/nature22994"},{"key":"ref12","year":"0"},{"key":"ref13","article-title":"A 7 nm 4GHz Arm&#x00AE;-core-based CoWoS&#x00AE; Chiplet Design for High Performance Computing","author":"lin","year":"2019","journal-title":"VLSI circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED52811.2021.9502481"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2952282"},{"key":"ref16","article-title":"Foundry Solutions for 2.5D\/3D Integration","author":"yu","year":"2021","journal-title":"ISSCC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00091"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00055"},{"key":"ref19","article-title":"Stack up your chips: Betting on 3D integration to augment Moore's Law scaling","author":"sinha","year":"2019","journal-title":"S3S"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/NVMTS.2018.8603104"},{"key":"ref6","article-title":"Case Study: AMD products built with 3D packaging","author":"swaminathan","year":"2021","journal-title":"HCS"},{"key":"ref5","article-title":"XeHPC Ponte Vecchio","author":"blythe","year":"2021","journal-title":"HCS"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2016.65"},{"key":"ref7","article-title":"TSMC packaging technologies for chiplets and 3D","author":"yu","year":"2021","journal-title":"HCS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2017.7939084"},{"key":"ref1","article-title":"The State-of-the-Art of Smartphone Imagers","author":"fontaine","year":"2019","journal-title":"IISW"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"ref20","article-title":"APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors","author":"xie","year":"2021","journal-title":"Micro"},{"key":"ref21","article-title":"Enhanced 3D Implementation of an Arm(R) Cortex's-A Microprocessor","author":"xu","year":"2019","journal-title":"ISLPED"}],"event":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","location":"Newport Beach, CA, USA","start":{"date-parts":[[2022,4,24]]},"end":{"date-parts":[[2022,4,27]]}},"container-title":["2022 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9772767\/9772730\/09772831.pdf?arnumber=9772831","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T20:58:05Z","timestamp":1656363485000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9772831\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/cicc53496.2022.9772831","relation":{},"subject":[],"published":{"date-parts":[[2022,4]]}}}