{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T02:15:13Z","timestamp":1777601713609,"version":"3.51.4"},"reference-count":58,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,4]]},"DOI":"10.1109\/cicc53496.2022.9772842","type":"proceedings-article","created":{"date-parts":[[2022,5,18]],"date-time":"2022-05-18T19:37:56Z","timestamp":1652902676000},"page":"1-7","source":"Crossref","is-referenced-by-count":16,"title":["Recent Advances in High-Performance Frequency Synthesizer Design"],"prefix":"10.1109","author":[{"given":"Salvatore","family":"Levantino","sequence":"first","affiliation":[{"name":"Politecnico di Milano,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2477575"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2064050"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157259"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2763581"},{"key":"ref31","first-page":"266","article-title":"A -240dB- FoMjtter and -115dBc\/Hz PN 100 kHz, 7.7 GHz ring-DCO-based digital PLL using P\/I-gain co-optimization and sequence-rearranged optimally spaced TDC for flicker-noise reduction","author":"lee","year":"2020","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2495725"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2435691"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"821","DOI":"10.1109\/JSSC.2016.2519391","article-title":"A bang bang phase-locked loop using automatic loop gain control and loop latency reduction techniques","volume":"51","author":"kuan","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2423793"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231354"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3019344"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2940332"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1049\/el.2016.4577"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"2745","DOI":"10.1109\/JSSC.2011.2162917","article-title":"A 2.9–4.0-GHz fractional-N digital PLL with bang-bang phase detector and 560-fsrms integrated jitter at 4.5-mW power","volume":"46","author":"tasca","year":"0","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598309"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185190"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3116860"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361351"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168691"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310279"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2993717"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2018.8428846"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3111134"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492419"},{"key":"ref57","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking Figure-of-Merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939663"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2414421"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365798"},{"key":"ref53","article-title":"A 4GHz 0.73psrms-lntegrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC","author":"jung","year":"2020","journal-title":"Proc Symp VLSI Circuits (VLSI Circuits)"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2941259"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2239114"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3123827"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3072344"},{"key":"ref14","first-page":"396","article-title":"A-242 dB FOM and -75 dBc reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC","author":"seong","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","first-page":"258","article-title":"A 76 fsrms jitter and -40 dBc integrated-phase-noise 28-to-31GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization","author":"kim","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2959252"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2361523"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063114"},{"key":"ref4","author":"da dalt","year":"2007","journal-title":"Theory and Implementation of Digital Bang-bang Frequency Synthesizers for High Speed Serial Data Communications"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"3663","DOI":"10.1109\/TCSI.2008.925948","article-title":"Linearized analysis of a digital bang-bang PLL and its validity limits applied to jitter transfer and jitter generation","volume":"55","author":"da","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.883197"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2104270"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062948"},{"key":"ref9","first-page":"174","article-title":"A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, Digital Fractional-N Sampling PLL in 28nm CMOS","author":"gao","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref46","first-page":"54","article-title":"A back-ground calibration technique to control bandwidth in digital PLLs","author":"marzin","year":"2014","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2548258"},{"key":"ref48","article-title":"A 3.7-to-4.1 GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter","author":"mercandelli","year":"2021","journal-title":"Proc Asian Solid-State Circuits Conf (ASSCC)"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2866454"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2010792"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2179733"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/4.974542"},{"key":"ref43","first-page":"3401","article-title":"A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop","author":"lee","year":"2010","journal-title":"Proc IEEE Int Symp Circuits Syst"}],"event":{"name":"2022 IEEE Custom Integrated Circuits Conference (CICC)","location":"Newport Beach, CA, USA","start":{"date-parts":[[2022,4,24]]},"end":{"date-parts":[[2022,4,27]]}},"container-title":["2022 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9772767\/9772730\/09772842.pdf?arnumber=9772842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,27]],"date-time":"2022-06-27T20:58:00Z","timestamp":1656363480000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9772842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4]]},"references-count":58,"URL":"https:\/\/doi.org\/10.1109\/cicc53496.2022.9772842","relation":{},"subject":[],"published":{"date-parts":[[2022,4]]}}}