{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,30]],"date-time":"2025-08-30T16:22:16Z","timestamp":1756570936716},"reference-count":5,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.1109\/cicc57935.2023.10121322","type":"proceedings-article","created":{"date-parts":[[2023,5,11]],"date-time":"2023-05-11T13:23:55Z","timestamp":1683811435000},"page":"1-2","source":"Crossref","is-referenced-by-count":5,"title":["A 0.99\u03bcs FFT-Based Fast-Locking, 0.82GHz-to-4.1GHz DPLL-Based Input-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces"],"prefix":"10.1109","author":[{"given":"Woosong","family":"Jung","sequence":"first","affiliation":[{"name":"Seoul National University,Seoul,Korea"}]},{"given":"Hyojun","family":"Kim","sequence":"additional","affiliation":[{"name":"Seoul National University,Seoul,Korea"}]},{"given":"Yeonggeun","family":"Song","sequence":"additional","affiliation":[{"name":"Seoul National University,Seoul,Korea"}]},{"given":"Kwang-Hoon","family":"Lee","sequence":"additional","affiliation":[{"name":"Seoul National University,Seoul,Korea"}]},{"given":"Deog-Kyoon","family":"Jeong","sequence":"additional","affiliation":[{"name":"Seoul National University,Seoul,Korea"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310279"},{"key":"ref3","article-title":"Analysis of a 28-nm CMOS Fast-Lock BangBang Digital PLL with 220-fs RMS Jitter for Millimeter-Wave Communication","author":"tsai","year":"2020","journal-title":"JSSC"},{"key":"ref5","article-title":"17.2 A 66fsrmsJitter 12.8-to-15.2 GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking","author":"santiccioli","year":"2020","journal-title":"ISSCC"},{"key":"ref2","article-title":"A 18.6-to-40.1 GHz 201.7dBc\/Hz FoMT Multi-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting","author":"shu","year":"2020","journal-title":"ISSCC"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431447"}],"event":{"name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","start":{"date-parts":[[2023,4,23]]},"location":"San Antonio, TX, USA","end":{"date-parts":[[2023,4,26]]}},"container-title":["2023 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10121189\/10121178\/10121322.pdf?arnumber=10121322","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T12:58:10Z","timestamp":1685710690000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10121322\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/cicc57935.2023.10121322","relation":{},"subject":[],"published":{"date-parts":[[2023,4]]}}}