{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T05:08:47Z","timestamp":1769922527946,"version":"3.49.0"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,4,13]],"date-time":"2025-04-13T00:00:00Z","timestamp":1744502400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,13]],"date-time":"2025-04-13T00:00:00Z","timestamp":1744502400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,4,13]]},"DOI":"10.1109\/cicc63670.2025.10983098","type":"proceedings-article","created":{"date-parts":[[2025,5,19]],"date-time":"2025-05-19T17:52:03Z","timestamp":1747677123000},"page":"1-3","source":"Crossref","is-referenced-by-count":2,"title":["A 17.4fJ\/conv.-step, 202\u00b5m<sup>2<\/sup>, 1.5GS\/s and PVT-Tolerant 7-Bit Charge-Injection SAR ADC in 28nm CMOS Using a Background-Calibrated 1-Bit Metastability Detector and a gm-Boosted StrongARM Comparator"],"prefix":"10.1109","author":[{"given":"Chaeeun","family":"Lee","sequence":"first","affiliation":[{"name":"Konkuk University,Seoul,Korea"}]},{"given":"Jongho","family":"Kim","sequence":"additional","affiliation":[{"name":"Konkuk University,Seoul,Korea"}]},{"given":"Jintae","family":"Kim","sequence":"additional","affiliation":[{"name":"Konkuk University,Seoul,Korea"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/a-sscc58667.2023.10347948"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc55480.2022.9911287"},{"key":"ref3","article-title":"A 7GHz ERBW 1.1 GS\/s 6-bit PVT Tolerant Asynchronous CI-SAR with only 8.5fF Input Capacitance","author":"Kim","year":"2023","journal-title":"CICC"},{"key":"ref4","article-title":"Area-efficient 1 GS\/s 6b SAR ADC with charge-injection-cell-based DAC","author":"Choo","year":"2016","journal-title":"ISSCC"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2018.2822823"},{"key":"ref6","article-title":"A 3.1 mW 8b 1.2GS\/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOl CMOS","author":"Kull","year":"2013","journal-title":"ISSCC"},{"issue":"10","key":"ref7","article-title":"A 1.5-GS\/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS","volume":"69","author":"Lee","year":"2022","journal-title":"TCSI"},{"key":"ref8","article-title":"An 8b 1 GS\/s SAR ADC with Metastability-Based Resolution\/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input","author":"Li","year":"2024","journal-title":"CICC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2020.3017229"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2017.2768404"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc.2017.8094553"}],"event":{"name":"2025 IEEE Custom Integrated Circuits Conference (CICC)","location":"Boston, MA, USA","start":{"date-parts":[[2025,4,13]]},"end":{"date-parts":[[2025,4,17]]}},"container-title":["2025 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10982532\/10982698\/10983098.pdf?arnumber=10983098","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,20]],"date-time":"2025-05-20T09:39:25Z","timestamp":1747733965000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10983098\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,13]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/cicc63670.2025.10983098","relation":{},"subject":[],"published":{"date-parts":[[2025,4,13]]}}}