{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T16:21:49Z","timestamp":1759335709309,"version":"3.41.0"},"reference-count":34,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,4,13]],"date-time":"2025-04-13T00:00:00Z","timestamp":1744502400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,13]],"date-time":"2025-04-13T00:00:00Z","timestamp":1744502400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100013327","name":"IBM Research AI Hardware Center","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100013327","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,4,13]]},"DOI":"10.1109\/cicc63670.2025.10983594","type":"proceedings-article","created":{"date-parts":[[2025,5,19]],"date-time":"2025-05-19T17:52:03Z","timestamp":1747677123000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited)"],"prefix":"10.1109","author":[{"given":"G. W.","family":"Burr","sequence":"first","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"H.","family":"Tsai","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"I.","family":"Boybat","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"W. A.","family":"Simon","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"J.","family":"B\u00fcchel","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"A.","family":"Vasilopoulos","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"P.","family":"Narayanan","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"A.","family":"Fasoli","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"K.","family":"Hosokawa","sequence":"additional","affiliation":[{"name":"IBM Tokyo Research Laboratory,Tokyo,Japan"}]},{"given":"M.","family":"Le Gallo","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"M.","family":"Ishii","sequence":"additional","affiliation":[{"name":"IBM Tokyo Research Laboratory,Tokyo,Japan"}]},{"given":"Y.","family":"Kohda","sequence":"additional","affiliation":[{"name":"IBM Tokyo Research Laboratory,Tokyo,Japan"}]},{"given":"A.","family":"Okazaki","sequence":"additional","affiliation":[{"name":"IBM Tokyo Research Laboratory,Tokyo,Japan"}]},{"given":"A.","family":"Chen","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"C.","family":"Mackin","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"E.","family":"Ferro","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"K.","family":"El Maghraoui","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;T. J. Watson Research Center,Yorktown Heights,NY,USA"}]},{"given":"H.","family":"Benmeziane","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"T.","family":"Philicelli","sequence":"additional","affiliation":[{"name":"IBM Albany NanoTech,Albany,NY,USA"}]},{"given":"C.","family":"Lammie","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"A. M.","family":"Friz","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"J.","family":"Luquin","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Almaden,San Jose,CA,USA"}]},{"given":"S.","family":"Jain","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;T. J. Watson Research Center,Yorktown Heights,NY,USA"}]},{"given":"A.","family":"Sebastian","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;Zurich,R&#x00FC;schlikon,Switzerland"}]},{"given":"V.","family":"Narayanan","sequence":"additional","affiliation":[{"name":"IBM Research&#x2013;T. J. Watson Research Center,Yorktown Heights,NY,USA"}]}],"member":"263","reference":[{"key":"ref1","article-title":"Imagenet classification with deep convolutional neural networks","volume-title":"Adv. Neur. Inf. Proc. Sys.","volume":"25","author":"Krizhevsky","year":"2012"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1706.03762"},{"volume-title":"Language Models are Few-Shot Learners","year":"2020","author":"Brown","key":"ref3"},{"volume-title":"AI and Compute","author":"Amodei","key":"ref4"},{"key":"ref5","first-page":"1737","article-title":"Deep Learning with Limited Numerical Precision","volume-title":"ICML","author":"Gupta","year":"2015"},{"issue":"1","key":"ref6","first-page":"10882","article-title":"Sparsity in deep learning: Pruning and growth for efficient inference and training in neural networks","volume":"22","author":"Hoefler","year":"2021","journal-title":"J. Mach. Learn. Res."},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2021.9641759"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2022.3210152"},{"key":"ref10","first-page":"260","article-title":"Analog matrix processor for edge AI real-time video analvtics","volume-title":"ISSCC","volume":"65","author":"Fick","year":"2022"},{"key":"ref11","first-page":"1","article-title":"A 40nm 100Kb 118.44 TOPS\/W Ternary-weight Compute-in-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation","volume-title":"CICC","author":"Yoon","year":"2021"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3115993"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3140414"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/B978-0-12-820758-1.00005-4"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067666"},{"volume-title":"BERT: Pre-training of deep bidirectional transformers for lanauaae understanding","year":"2018","author":"Devlin","key":"ref16"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3221390"},{"volume-title":"Outrageously large neural networks: The sparselygated","year":"2017","author":"Shazeer","key":"ref19"},{"volume-title":"Mixtral of experts.","year":"2024","key":"ref20"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/s43588-024-00753-x"},{"volume-title":"Generating long sequences with sparse transformers","year":"2019","author":"Child","key":"ref22"},{"key":"ref23","first-page":"606","article-title":"Efficiently scaling transformer inference","volume-title":"Proceedings of Machine Learning and Systems","volume":"5","author":"Pope","year":"2023"},{"key":"ref24","article-title":"Design of Analog-Al Hardware Accelerators for","volume-title":"IEDM 2023","author":"Burr","year":"2023"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1126\/science.adh1174"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC62836.2024.10938418"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3063366"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-023-06337-5"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2017.2716579"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-023-01010-1"},{"key":"ref31","first-page":"144","article-title":"9.1 A 7nm 4-Core Al Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttllnq","volume-title":"ISSCC","volume":"64","author":"Agrawal","year":"2021"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-023-40770-4"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3119018"},{"key":"ref34","article-title":"Heterogeneous Embedded Neural Processing Units utilizino PCM-based Analog In-Memory Computing","volume-title":"IEDM 2024","author":"Boybat","year":"2024"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.18653\/v1\/2023.emnlp-main.298"}],"event":{"name":"2025 IEEE Custom Integrated Circuits Conference (CICC)","start":{"date-parts":[[2025,4,13]]},"location":"Boston, MA, USA","end":{"date-parts":[[2025,4,17]]}},"container-title":["2025 IEEE Custom Integrated Circuits Conference (CICC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10982532\/10982698\/10983594.pdf?arnumber=10983594","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,20]],"date-time":"2025-05-20T09:52:44Z","timestamp":1747734764000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10983594\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,13]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/cicc63670.2025.10983594","relation":{},"subject":[],"published":{"date-parts":[[2025,4,13]]}}}