{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T13:05:08Z","timestamp":1730207108762,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,10]]},"DOI":"10.1109\/cisim.2010.5643683","type":"proceedings-article","created":{"date-parts":[[2010,11,30]],"date-time":"2010-11-30T21:34:10Z","timestamp":1291152850000},"page":"90-95","source":"Crossref","is-referenced-by-count":3,"title":["Analysis of digital DSP blocks using GDI technology"],"prefix":"10.1109","author":[{"given":"Mehdi","family":"Faed","sequence":"first","affiliation":[]},{"given":"Mohammad","family":"Mortazavi","sequence":"additional","affiliation":[]},{"given":"Alireza","family":"Faed","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"44","article-title":"CMOS Technology: Challenges for Future Development","author":"wanlass","year":"1991","journal-title":"IEEE Spectrum"},{"key":"ref11","article-title":"A Novel Low-Power low-voltage CMOS 1-BIT Full Adder Cell with the GDI Technique","author":"saberkari","year":"0","journal-title":"Proceedings of the 2006 IJME"},{"key":"ref12","first-page":"590","author":"rabaey","year":"2006","journal-title":"Digital Integrated Circuits"},{"year":"0","key":"ref13"},{"key":"ref14","article-title":"Ultr a Low Power Full Adder Topologies","author":"moradi","year":"2009","journal-title":"San Francisco State Univ"},{"key":"ref15","article-title":"Design and Implementation of Full Adder Cell With the GDI Technique Based on 0.18µm CMOS Technology","author":"bazzazi","year":"0","journal-title":"IMECS 2010"},{"journal-title":"IEEE 2006","article-title":"Low Power Digital Design Using Modified GDI Method","year":"0","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2001.954670"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.801578"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1009881"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831474"},{"key":"ref7","article-title":"GDI (Gate Diffusion Input) Circuits for Fast and Low-Power Implementations of Logical Gates","volume":"751","author":"morgenshtein","year":"2003"},{"key":"ref2","first-page":"304","author":"weste","year":"0","journal-title":"Principles of CMOS digital design"},{"article-title":"Digital Integrated Circuits","year":"2002","author":"rabaey","key":"ref1"},{"key":"ref9","article-title":"Gate-Diffusion Input (GDI) Technology for Area-Efficient Digital Circuits Implementations in Standard Fabrication Technologies","author":"morgenshtein","year":"2005","journal-title":"US Patent Application"}],"event":{"name":"2010 International Conference on Computer Information Systems and Industrial Management Applications (CISIM)","start":{"date-parts":[[2010,10,8]]},"location":"Krackow, Poland","end":{"date-parts":[[2010,10,10]]}},"container-title":["2010 International Conference on Computer Information Systems and Industrial Management Applications (CISIM)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5637902\/5643452\/05643683.pdf?arnumber=5643683","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T08:39:24Z","timestamp":1490085564000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5643683\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/cisim.2010.5643683","relation":{},"subject":[],"published":{"date-parts":[[2010,10]]}}}