{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:46:57Z","timestamp":1725551217812},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,7]]},"DOI":"10.1109\/cit.2008.4594790","type":"proceedings-article","created":{"date-parts":[[2008,8,13]],"date-time":"2008-08-13T18:40:13Z","timestamp":1218652813000},"page":"880-885","source":"Crossref","is-referenced-by-count":0,"title":["Layer assignment considering manufacturability in X-architecture clock tree"],"prefix":"10.1109","author":[{"family":"Chia-Chun Tsai","sequence":"first","affiliation":[]},{"family":"Wei-Shi Lin","sequence":"additional","affiliation":[]},{"family":"Jan-Ou Wu","sequence":"additional","affiliation":[]},{"family":"Chung-Chieh Kuo","sequence":"additional","affiliation":[]},{"family":"Trong-Yen Lee","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.830932"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147101"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.881822"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2005.67"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118376"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123037"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2002.1043334"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/82.204128"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884492"},{"key":"7","first-page":"768","article-title":"physical cad changes to incorporate design for lithography and manufacturability","author":"scheffer","year":"2004","journal-title":"Proc ASP-DAC"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357992"},{"key":"5","first-page":"2081","article-title":"high performance clock routing in x-architecture","author":"shen","year":"2006","journal-title":"Proc ISCAS"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560133"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCAS.2006.285166"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065678"}],"event":{"name":"2008 8th IEEE International Conference on Computer and Information Technology (CIT)","start":{"date-parts":[[2008,7,8]]},"location":"Sydney, Australia","end":{"date-parts":[[2008,7,11]]}},"container-title":["2008 8th IEEE International Conference on Computer and Information Technology"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4586225\/4594630\/04594790.pdf?arnumber=4594790","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T11:48:17Z","timestamp":1489664897000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4594790\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,7]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/cit.2008.4594790","relation":{},"subject":[],"published":{"date-parts":[[2008,7]]}}}