{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:59:02Z","timestamp":1759334342991,"version":"build-2065373602"},"reference-count":4,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T00:00:00Z","timestamp":1756771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,2]],"date-time":"2025-09-02T00:00:00Z","timestamp":1756771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100006559","name":"University of Tsukuba","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100006559","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,9,2]]},"DOI":"10.1109\/clusterworkshops65972.2025.11164213","type":"proceedings-article","created":{"date-parts":[[2025,9,22]],"date-time":"2025-09-22T17:42:49Z","timestamp":1758562969000},"page":"1-2","source":"Crossref","is-referenced-by-count":0,"title":["GPU-CPU Shared Memory Performance Analysis on NVIDIA GH200"],"prefix":"10.1109","author":[{"given":"Norihisa","family":"Fujita","sequence":"first","affiliation":[{"name":"University of Tsukuba,Center for Computational Sciences,Tsukuba,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taisuke","family":"Boku","sequence":"additional","affiliation":[{"name":"University of Tsukuba,Center for Computational Sciences,Tsukuba,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomo","family":"Yoshida","sequence":"additional","affiliation":[{"name":"University of Tsukuba,Degree Programs in Systems and Information Engineering,Tsukuba,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takuto","family":"Shirai","sequence":"additional","affiliation":[{"name":"University of Tsukuba,Degree Programs in Systems and Information Engineering,Tsukuba,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Miwako","family":"Tsuji","sequence":"additional","affiliation":[{"name":"University of Tsukuba,Center for Computational Sciences,Tsukuba,Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"volume-title":"NVIDIA Grace Hopper Superchip Architecture whitepaper","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3673038.3673110"},{"volume-title":"Miyabi Supercomputer","key":"ref3"},{"volume-title":"University of Tsukuba Pegasus - Big memory supercomputer","key":"ref4"}],"event":{"name":"2025 IEEE International Conference on Cluster Computing Workshops (CLUSTER Workshops)","start":{"date-parts":[[2025,9,2]]},"location":"Edinburgh, United Kingdom","end":{"date-parts":[[2025,9,5]]}},"container-title":["2025 IEEE International Conference on Cluster Computing Workshops (CLUSTER Workshops)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11163725\/11164191\/11164213.pdf?arnumber=11164213","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,30]],"date-time":"2025-09-30T15:01:40Z","timestamp":1759244500000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11164213\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9,2]]},"references-count":4,"URL":"https:\/\/doi.org\/10.1109\/clusterworkshops65972.2025.11164213","relation":{},"subject":[],"published":{"date-parts":[[2025,9,2]]}}}