{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:13:05Z","timestamp":1767262385229,"version":"3.37.3"},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,7,29]],"date-time":"2024-07-29T00:00:00Z","timestamp":1722211200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,7,29]],"date-time":"2024-07-29T00:00:00Z","timestamp":1722211200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,7,29]]},"DOI":"10.1109\/coins61597.2024.10622147","type":"proceedings-article","created":{"date-parts":[[2024,8,15]],"date-time":"2024-08-15T17:18:58Z","timestamp":1723742338000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["A User-Friendly Ecosystem for AI FPGA-Based Accelerators"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3263-7853","authenticated-orcid":false,"given":"Luis G.","family":"Leon-Vega","sequence":"first","affiliation":[{"name":"University of Trieste,MIGe Department,Trieste,Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-1046-0894","authenticated-orcid":false,"given":"Erick","family":"Obregon-Fonseca","sequence":"additional","affiliation":[{"name":"Electronics Engineering School, Costa Rica Institute of Technology,Cartago,Costa Rica"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4808-4904","authenticated-orcid":false,"given":"Jorge","family":"Castro-Godinez","sequence":"additional","affiliation":[{"name":"Electronics Engineering School, Costa Rica Institute of Technology,Cartago,Costa Rica"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446050"},{"volume-title":"XaaS: Acceleration as a Service to Enable Productive High-Performance Cloud Computing","year":"2024","author":"Hoefler","key":"ref2"},{"volume-title":"TOP 500: November 2023","year":"2023","key":"ref3"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2008.57"},{"volume-title":"Xilinx Runtime Library (XRT)","year":"2024","key":"ref5"},{"volume-title":"Vitis Unified Software Platform Documentation: Em-bedded Software Development (UG1400)","year":"2023","key":"ref6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3242897"},{"key":"ref8","first-page":"1","article-title":"A dynamic partial reconfigurable overlay concept for PYNQ","volume-title":"2017 27th International Conference on Field Programmable Logic and Applications (FPL)","author":"Jan\u03b2en"},{"volume-title":"Vitis Libraries","year":"2023","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3405794"},{"volume-title":"CYNQ (v0.2)","year":"2024","author":"G","key":"ref11"},{"key":"ref12","first-page":"1","article-title":"ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications","volume-title":"FSP Workshop 2018; Fifth International Workshop on FPGAs for Software Programmers","author":"Pham"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1088\/1748-0221\/13\/07\/P07027"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DCAS53974.2022.9845501"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3594540"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DSN-W58399.2023.00048"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/bip60195.2023.10379257"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1201\/9781003162810"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/567806.567807"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1137\/1.9780898719604"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/301618.301661"},{"volume-title":"CUDA Libraries","key":"ref22"},{"volume-title":"xfopencv - xilinx opencv library","year":"2019","key":"ref23"},{"volume-title":"Flexible Accelerator Library: Approximate Matrix Accelerator","year":"2023","author":"Leon-Vega","key":"ref24"},{"issue":"184","key":"ref25","article-title":"Completely fair scheduler","volume":"2009","author":"Pabla","year":"2009","journal-title":"Linux J."},{"volume-title":"AxC Kernel Delegate Interface","year":"2022","author":"Obreg\u00f3n-Fonseca","key":"ref26"},{"volume-title":"AxC Executer","year":"2024","author":"Le\u00f3n-Vega","key":"ref27"},{"volume-title":"Open-source FPGA-ML codesign for the MLPerf Tiny Benchmark","year":"2022","author":"Borras","key":"ref28"}],"event":{"name":"2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS)","start":{"date-parts":[[2024,7,29]]},"location":"London, United Kingdom","end":{"date-parts":[[2024,7,31]]}},"container-title":["2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10622105\/10622106\/10622147.pdf?arnumber=10622147","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,16]],"date-time":"2024-08-16T05:44:51Z","timestamp":1723787091000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10622147\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,29]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/coins61597.2024.10622147","relation":{},"subject":[],"published":{"date-parts":[[2024,7,29]]}}}