{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T22:37:11Z","timestamp":1729636631495,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,4]]},"DOI":"10.1109\/coolchips.2011.5890920","type":"proceedings-article","created":{"date-parts":[[2011,6,20]],"date-time":"2011-06-20T17:08:15Z","timestamp":1308589695000},"page":"1-3","source":"Crossref","is-referenced-by-count":1,"title":["An 80 Gbps dependable multicore communication SoC with PCI express I\/F and intelligent interrupt controller"],"prefix":"10.1109","author":[{"given":"Sugako","family":"Otani","sequence":"first","affiliation":[]},{"given":"Hiroyuki","family":"Kondo","sequence":"additional","affiliation":[]},{"given":"Itaru","family":"Nonomura","sequence":"additional","affiliation":[]},{"given":"Atsuyuki","family":"Ikeya","sequence":"additional","affiliation":[]},{"given":"Minoru","family":"Uemura","sequence":"additional","affiliation":[]},{"given":"Katsushi","family":"Asahina","sequence":"additional","affiliation":[]},{"given":"Kazutami","family":"Arimoto","sequence":"additional","affiliation":[]},{"given":"Shin'ichi","family":"Miura","sequence":"additional","affiliation":[]},{"given":"Toshihiro","family":"Hanawa","sequence":"additional","affiliation":[]},{"given":"Taisuke","family":"Boku","sequence":"additional","affiliation":[]},{"given":"Mitsuhisa","family":"Sato","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820866"},{"journal-title":"PCI-SIG","article-title":"PCI Express Base Specification, Rev. 2.0","year":"0","key":"ref3"},{"journal-title":"InfiniBand Trade Association","article-title":"The InfiniBand architecture specification","year":"0","key":"ref6"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"892","DOI":"10.1109\/JSSC.2008.917528","article-title":"Design and Implementation of a Configurable Heterogeneous Multicore SoC With 9 CPUs and 2 Matrix Processors","volume":"43","author":"kondo","year":"0","journal-title":"IEEE Journal of Solid-State Circuits"},{"journal-title":"http \/\/www qlogic com\/","article-title":"QLogic TrueScale&#x2122; InfiniBand, the Real Value","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746312"},{"key":"ref1","article-title":"Low-power and high-performance communication mechanism for dependable embedded systems","author":"hanawa","year":"2009","journal-title":"Proceedings of 2008 International Workshop on Innovative Architecture for Future Generation Processors and Systems"}],"event":{"name":"2011 IEEE Cool Chips XIV","start":{"date-parts":[[2011,4,20]]},"location":"Yokohama, Japan","end":{"date-parts":[[2011,4,22]]}},"container-title":["2011 IEEE Cool Chips XIV"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5871805\/5890901\/05890920.pdf?arnumber=5890920","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T21:50:26Z","timestamp":1497909026000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5890920\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,4]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/coolchips.2011.5890920","relation":{},"subject":[],"published":{"date-parts":[[2011,4]]}}}